linux-kernel - Re: [PATCH v3 2/3] pinctrl: add pinctrl driver on mt8186

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Message-ID: <4f7fe0940c03f6fba7096b4e1c9239167a5906f7.camel@mediatek.com>
Date:   Mon, 14 Feb 2022 11:02:52 +0800
From:   Guodong Liu <guodong.liu@...iatek.com>
To:     AngeloGioacchino Del Regno 
        <angelogioacchino.delregno@...labora.com>,
        Linus Walleij <linus.walleij@...aro.org>,
        Rob Herring <robh+dt@...nel.org>,
        Matthias Brugger <matthias.bgg@...il.com>,
        Sean Wang <sean.wang@...nel.org>
CC:     Sean Wang <sean.wang@...iatek.com>, <linux-gpio@...r.kernel.org>,
        <devicetree@...r.kernel.org>,
        <linux-arm-kernel@...ts.infradead.org>,
        <linux-mediatek@...ts.infradead.org>,
        <linux-kernel@...r.kernel.org>,
        <Project_Global_Chrome_Upstream_Group@...iatek.com>
Subject: Re: [PATCH v3 2/3] pinctrl: add pinctrl driver on mt8186

-----Original Message-----
From: AngeloGioacchino Del Regno <
angelogioacchino.delregno@...labora.com>
To: Guodong Liu <guodong.liu@...iatek.com>, Linus Walleij <
linus.walleij@...aro.org>, Rob Herring <robh+dt@...nel.org>, Matthias
Brugger <matthias.bgg@...il.com>, Sean Wang <sean.wang@...nel.org>
Cc: Sean Wang <sean.wang@...iatek.com>, linux-gpio@...r.kernel.org, 
devicetree@...r.kernel.org, linux-arm-kernel@...ts.infradead.org, 
linux-mediatek@...ts.infradead.org, linux-kernel@...r.kernel.org, 
Project_Global_Chrome_Upstream_Group@...iatek.com
Subject: Re: [PATCH v3 2/3] pinctrl: add pinctrl driver on mt8186
Date: Thu, 10 Feb 2022 09:57:03 +0100

Il 10/02/22 07:21, Guodong Liu ha scritto:
> This commit includes pinctrl driver for mt8186.
> 
> Signed-off-by: Guodong Liu <guodong.liu@...iatek.com>
> ---
>   drivers/pinctrl/mediatek/Kconfig              |    7 +
>   drivers/pinctrl/mediatek/Makefile             |    1 +
>   drivers/pinctrl/mediatek/pinctrl-mt8186.c     | 1313 ++++++++++
>   drivers/pinctrl/mediatek/pinctrl-mtk-mt8186.h | 2186
> +++++++++++++++++
>   4 files changed, 3507 insertions(+)
>   create mode 100644 drivers/pinctrl/mediatek/pinctrl-mt8186.c
>   create mode 100644 drivers/pinctrl/mediatek/pinctrl-mtk-mt8186.h
> 
> diff --git a/drivers/pinctrl/mediatek/Kconfig
> b/drivers/pinctrl/mediatek/Kconfig
> index 66db4ac5d169..8dca1ef04965 100644
> --- a/drivers/pinctrl/mediatek/Kconfig
> +++ b/drivers/pinctrl/mediatek/Kconfig
> @@ -147,6 +147,13 @@ config PINCTRL_MT8183
>   	default ARM64 && ARCH_MEDIATEK
>   	select PINCTRL_MTK_PARIS
>   
> +config PINCTRL_MT8186
> +	bool "Mediatek MT8186 pin control"
> +	depends on OF
> +	depends on ARM64 || COMPILE_TEST
> +	default ARM64 && ARCH_MEDIATEK
> +	select PINCTRL_MTK_PARIS
> +
>   config PINCTRL_MT8192
>   	bool "Mediatek MT8192 pin control"
>   	depends on OF
> diff --git a/drivers/pinctrl/mediatek/Makefile
> b/drivers/pinctrl/mediatek/Makefile
> index 90f43bb9d9a7..31c3784c6089 100644
> --- a/drivers/pinctrl/mediatek/Makefile
> +++ b/drivers/pinctrl/mediatek/Makefile
> @@ -21,6 +21,7 @@ obj-$(CONFIG_PINCTRL_MT7986)	+= pinctrl-
> mt7986.o
>   obj-$(CONFIG_PINCTRL_MT8167)	+= pinctrl-mt8167.o
>   obj-$(CONFIG_PINCTRL_MT8173)	+= pinctrl-mt8173.o
>   obj-$(CONFIG_PINCTRL_MT8183)	+= pinctrl-mt8183.o
> +obj-$(CONFIG_PINCTRL_MT8186)	+= pinctrl-mt8186.o
>   obj-$(CONFIG_PINCTRL_MT8192)	+= pinctrl-mt8192.o
>   obj-$(CONFIG_PINCTRL_MT8195)    += pinctrl-mt8195.o
>   obj-$(CONFIG_PINCTRL_MT8365)	+= pinctrl-mt8365.o
> diff --git a/drivers/pinctrl/mediatek/pinctrl-mt8186.c
> b/drivers/pinctrl/mediatek/pinctrl-mt8186.c
> new file mode 100644
> index 000000000000..1e550b15b9d4
> --- /dev/null
> +++ b/drivers/pinctrl/mediatek/pinctrl-mt8186.c
> @@ -0,0 +1,1313 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * Copyright (C) 2021 MediaTek Inc.
> + *
> + * Author: Guodong Liu <guodong.liu@...iatek.com>
> + *
> + */
> +
> +#include "pinctrl-mtk-mt8186.h"
> +#include "pinctrl-paris.h"
> +
> +/* MT8186 have multiple bases to program pin configuration listed as
> the below:
> + * iocfg[0]:0x10005000, iocfg[1]:0x10002000, iocfg[2]:0x10002200,
> + * iocfg[3]:0x10002400, iocfg[4]:0x10002600, iocfg[5]:0x10002800,
> + * iocfg[6]:0x10002C00.
> + * _i_based could be used to indicate what base the pin should be
> mapped into.
> + */
> +
> +#define PIN_FIELD_BASE(s_pin, e_pin, i_base, s_addr, x_addrs, s_bit,
> x_bits) \
> +	PIN_FIELD_CALC(s_pin, e_pin, i_base, s_addr, x_addrs, s_bit,
> x_bits, \
> +		       32, 0)

Please don't break this line: 84 columns is fine.

Hi Angelo

we will update it for next version.

Thanks
Guodong
> +
> +#define PINS_FIELD_BASE(s_pin, e_pin, i_base, s_addr, x_addrs,
> s_bit, x_bits) \
> +	PIN_FIELD_CALC(s_pin, e_pin, i_base, s_addr, x_addrs, s_bit,
> x_bits,  \
> +		       32, 1)

Same here.

Hi Angelo

we will update it for next version.

Thanks
Guodong
And with that fixed,
Reviewed-by: AngeloGioacchino Del Regno <
angelogioacchino.delregno@...labora.com>