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Message-ID: <20220214084455.GF3494@thinkpad>
Date: Mon, 14 Feb 2022 14:14:55 +0530
From: Manivannan Sadhasivam <manivannan.sadhasivam@...aro.org>
To: Rohit Agarwal <quic_rohiagar@...cinc.com>
Cc: agross@...nel.org, bjorn.andersson@...aro.org, robh+dt@...nel.org,
linux-arm-msm@...r.kernel.org, devicetree@...r.kernel.org,
linux-kernel@...r.kernel.org
Subject: Re: [PATCH 6/8] ARM: dts: qcom: sdx65: Add support for APCS block
On Mon, Feb 14, 2022 at 12:32:17PM +0530, Rohit Agarwal wrote:
> The APCS block on SDX65 acts as a mailbox controller and also provides
> clock output for the Cortex A7 CPU.
>
> Signed-off-by: Rohit Agarwal <quic_rohiagar@...cinc.com>
Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@...aro.org>
Thanks,
Mani
> ---
> arch/arm/boot/dts/qcom-sdx65.dtsi | 9 +++++++++
> 1 file changed, 9 insertions(+)
>
> diff --git a/arch/arm/boot/dts/qcom-sdx65.dtsi b/arch/arm/boot/dts/qcom-sdx65.dtsi
> index 2900ffe..1646c7c 100644
> --- a/arch/arm/boot/dts/qcom-sdx65.dtsi
> +++ b/arch/arm/boot/dts/qcom-sdx65.dtsi
> @@ -133,6 +133,15 @@
> #clock-cells = <0>;
> };
>
> + apcs: mailbox@...10000 {
> + compatible = "qcom,sdx65-apcs-gcc", "syscon";
> + reg = <0x17810000 0x2000>;
> + #mbox-cells = <1>;
> + clocks = <&rpmhcc RPMH_CXO_CLK>, <&a7pll>, <&gcc GPLL0>;
> + clock-names = "ref", "pll", "aux";
> + #clock-cells = <0>;
> + };
> +
> timer@...20000 {
> #address-cells = <1>;
> #size-cells = <1>;
> --
> 2.7.4
>
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