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Date: Mon, 14 Feb 2022 17:38:33 +0800
From: kernel test robot <lkp@...el.com>
To: Emil Renner Berthing <kernel@...il.dk>
Cc: kbuild-all@...ts.01.org, linux-kernel@...r.kernel.org
Subject: [esmil:visionfive 60/64]
drivers/soc/sifive/sifive_l2_cache.c:158:17: error: implicit declaration of
function 'writeq'; did you mean 'writel'?
Hi Emil,
First bad commit (maybe != root cause):
tree: https://github.com/esmil/linux visionfive
head: a29d7d9e1f688baf4c70b3a1d2244193e3323e0d
commit: d9a4a3d985ace9a7d6edd6f60ed765443f0c8ae5 [60/64] RISC-V: Enable SIFIVE_L2_FLUSH for StarFive SoCs
config: riscv-randconfig-r031-20220213 (https://download.01.org/0day-ci/archive/20220214/202202141742.K9YE1JCn-lkp@intel.com/config)
compiler: riscv32-linux-gcc (GCC) 11.2.0
reproduce (this is a W=1 build):
wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross
chmod +x ~/bin/make.cross
# https://github.com/esmil/linux/commit/d9a4a3d985ace9a7d6edd6f60ed765443f0c8ae5
git remote add esmil https://github.com/esmil/linux
git fetch --no-tags esmil visionfive
git checkout d9a4a3d985ace9a7d6edd6f60ed765443f0c8ae5
# save the config file to linux build tree
mkdir build_dir
COMPILER_INSTALL_PATH=$HOME/0day COMPILER=gcc-11.2.0 make.cross O=build_dir ARCH=riscv SHELL=/bin/bash drivers/soc/sifive/
If you fix the issue, kindly add following tag as appropriate
Reported-by: kernel test robot <lkp@...el.com>
All errors (new ones prefixed by >>):
drivers/soc/sifive/sifive_l2_cache.c: In function 'sifive_l2_flush64_range':
>> drivers/soc/sifive/sifive_l2_cache.c:158:17: error: implicit declaration of function 'writeq'; did you mean 'writel'? [-Werror=implicit-function-declaration]
158 | writeq(line, l2_base + SIFIVE_L2_FLUSH64);
| ^~~~~~
| writel
cc1: some warnings being treated as errors
vim +158 drivers/soc/sifive/sifive_l2_cache.c
a967a289f16969 arch/riscv/mm/sifive_l2_cache.c Yash Shah 2019-05-06 126
9ca187fca0e9da drivers/soc/sifive/sifive_l2_cache.c Tom 2021-01-08 127 #ifdef CONFIG_SIFIVE_L2_FLUSH
9ca187fca0e9da drivers/soc/sifive/sifive_l2_cache.c Tom 2021-01-08 128 void sifive_l2_flush64_range(unsigned long start, unsigned long len)
9ca187fca0e9da drivers/soc/sifive/sifive_l2_cache.c Tom 2021-01-08 129 {
9ca187fca0e9da drivers/soc/sifive/sifive_l2_cache.c Tom 2021-01-08 130 unsigned long line;
9ca187fca0e9da drivers/soc/sifive/sifive_l2_cache.c Tom 2021-01-08 131
9ca187fca0e9da drivers/soc/sifive/sifive_l2_cache.c Tom 2021-01-08 132 if(!l2_base) {
9ca187fca0e9da drivers/soc/sifive/sifive_l2_cache.c Tom 2021-01-08 133 pr_warn("L2CACHE: base addr invalid, skipping flush\n");
9ca187fca0e9da drivers/soc/sifive/sifive_l2_cache.c Tom 2021-01-08 134 return;
9ca187fca0e9da drivers/soc/sifive/sifive_l2_cache.c Tom 2021-01-08 135 }
9ca187fca0e9da drivers/soc/sifive/sifive_l2_cache.c Tom 2021-01-08 136
9ca187fca0e9da drivers/soc/sifive/sifive_l2_cache.c Tom 2021-01-08 137 /* TODO: if (len == 0), skipping flush or going on? */
9ca187fca0e9da drivers/soc/sifive/sifive_l2_cache.c Tom 2021-01-08 138 if(!len) {
9ca187fca0e9da drivers/soc/sifive/sifive_l2_cache.c Tom 2021-01-08 139 pr_debug("L2CACHE: flush64 range @ 0x%lx(len:0)\n", start);
9ca187fca0e9da drivers/soc/sifive/sifive_l2_cache.c Tom 2021-01-08 140 return;
9ca187fca0e9da drivers/soc/sifive/sifive_l2_cache.c Tom 2021-01-08 141 }
9ca187fca0e9da drivers/soc/sifive/sifive_l2_cache.c Tom 2021-01-08 142
53c88578fe7510 drivers/soc/sifive/sifive_l2_cache.c Atish Patra 2021-06-12 143 len = len + (start % SIFIVE_L2_FLUSH64_LINE_LEN);
53c88578fe7510 drivers/soc/sifive/sifive_l2_cache.c Atish Patra 2021-06-12 144 start = ALIGN_DOWN(start, SIFIVE_L2_FLUSH64_LINE_LEN);
53c88578fe7510 drivers/soc/sifive/sifive_l2_cache.c Atish Patra 2021-06-12 145
9ca187fca0e9da drivers/soc/sifive/sifive_l2_cache.c Tom 2021-01-08 146 /* make sure the address is in the range */
9ca187fca0e9da drivers/soc/sifive/sifive_l2_cache.c Tom 2021-01-08 147 if(start < CONFIG_SIFIVE_L2_FLUSH_START ||
9ca187fca0e9da drivers/soc/sifive/sifive_l2_cache.c Tom 2021-01-08 148 (start + len) > (CONFIG_SIFIVE_L2_FLUSH_START +
9ca187fca0e9da drivers/soc/sifive/sifive_l2_cache.c Tom 2021-01-08 149 CONFIG_SIFIVE_L2_FLUSH_SIZE)) {
402885eef783d5 drivers/soc/sifive/sifive_l2_cache.c Geert Uytterhoeven 2021-05-21 150 WARN(1, "L2CACHE: flush64 out of range: %lx(%lx), skip flush\n",
9ca187fca0e9da drivers/soc/sifive/sifive_l2_cache.c Tom 2021-01-08 151 start, len);
9ca187fca0e9da drivers/soc/sifive/sifive_l2_cache.c Tom 2021-01-08 152 return;
9ca187fca0e9da drivers/soc/sifive/sifive_l2_cache.c Tom 2021-01-08 153 }
9ca187fca0e9da drivers/soc/sifive/sifive_l2_cache.c Tom 2021-01-08 154
9ca187fca0e9da drivers/soc/sifive/sifive_l2_cache.c Tom 2021-01-08 155 mb(); /* sync */
9ca187fca0e9da drivers/soc/sifive/sifive_l2_cache.c Tom 2021-01-08 156 for (line = start; line < start + len;
9ca187fca0e9da drivers/soc/sifive/sifive_l2_cache.c Tom 2021-01-08 157 line += SIFIVE_L2_FLUSH64_LINE_LEN) {
9ca187fca0e9da drivers/soc/sifive/sifive_l2_cache.c Tom 2021-01-08 @158 writeq(line, l2_base + SIFIVE_L2_FLUSH64);
9ca187fca0e9da drivers/soc/sifive/sifive_l2_cache.c Tom 2021-01-08 159 mb();
9ca187fca0e9da drivers/soc/sifive/sifive_l2_cache.c Tom 2021-01-08 160 }
9ca187fca0e9da drivers/soc/sifive/sifive_l2_cache.c Tom 2021-01-08 161 }
9ca187fca0e9da drivers/soc/sifive/sifive_l2_cache.c Tom 2021-01-08 162 EXPORT_SYMBOL_GPL(sifive_l2_flush64_range);
9ca187fca0e9da drivers/soc/sifive/sifive_l2_cache.c Tom 2021-01-08 163 #endif
9ca187fca0e9da drivers/soc/sifive/sifive_l2_cache.c Tom 2021-01-08 164
:::::: The code at line 158 was first introduced by commit
:::::: 9ca187fca0e9da3c005a260c74f75494eef2aa5f sifive/sifive_l2_cache: Add sifive_l2_flush64_range function
:::::: TO: Tom <support@...rs.com>
:::::: CC: Emil Renner Berthing <kernel@...il.dk>
---
0-DAY CI Kernel Test Service, Intel Corporation
https://lists.01.org/hyperkitty/list/kbuild-all@lists.01.org
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