linux-kernel - RE: [PATCH v1 5/7] drivers: fpga: dfl: handle empty port list

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Date:   Fri, 18 Feb 2022 08:24:50 +0000
From:   "Zhang, Tianfei" <tianfei.zhang@...el.com>
To:     Tom Rix <trix@...hat.com>, "Wu, Hao" <hao.wu@...el.com>,
        "mdf@...nel.org" <mdf@...nel.org>,
        "Xu, Yilun" <yilun.xu@...el.com>,
        "linux-fpga@...r.kernel.org" <linux-fpga@...r.kernel.org>,
        "linux-doc@...r.kernel.org" <linux-doc@...r.kernel.org>,
        "linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>
CC:     "corbet@....net" <corbet@....net>,
        Matthew Gerlach <matthew.gerlach@...ux.intel.com>
Subject: RE: [PATCH v1 5/7] drivers: fpga: dfl: handle empty port list



> -----Original Message-----
> From: Tom Rix <trix@...hat.com>
> Sent: Tuesday, February 15, 2022 11:56 PM
> To: Zhang, Tianfei <tianfei.zhang@...el.com>; Wu, Hao <hao.wu@...el.com>;
> mdf@...nel.org; Xu, Yilun <yilun.xu@...el.com>; linux-fpga@...r.kernel.org;
> linux-doc@...r.kernel.org; linux-kernel@...r.kernel.org
> Cc: corbet@....net; Matthew Gerlach <matthew.gerlach@...ux.intel.com>
> Subject: Re: [PATCH v1 5/7] drivers: fpga: dfl: handle empty port list
> 
> 
> On 2/14/22 3:26 AM, Tianfei zhang wrote:
> > From: Matthew Gerlach <matthew.gerlach@...ux.intel.com>
> >
> > Not all FPGA designs managed by the DFL driver have a port.
> > In these cases, don't write the Port Access Control register when
> > enabling SRIOV.
> 
> Drop the 'drivers:' in the subject line.

Yes, I agree.

> 
> This patch likely needs to moved to 4/7 since the last patch also iterated over
> the list.

Yes,  I agree, I will move it on next version patch.

> 
> Tom
> 
> >
> > Signed-off-by: Matthew Gerlach <matthew.gerlach@...ux.intel.com>
> > Signed-off-by: Tianfei Zhang <tianfei.zhang@...el.com>
> > ---
> >   drivers/fpga/dfl.c | 2 ++
> >   1 file changed, 2 insertions(+)
> >
> > diff --git a/drivers/fpga/dfl.c b/drivers/fpga/dfl.c index
> > cfc539a656f0..a5263ac258c5 100644
> > --- a/drivers/fpga/dfl.c
> > +++ b/drivers/fpga/dfl.c
> > @@ -1708,6 +1708,8 @@ int dfl_fpga_cdev_config_ports_vf(struct
> dfl_fpga_cdev *cdev, int num_vfs)
> >   	int ret = 0, port_count = 0;
> >
> >   	mutex_lock(&cdev->lock);
> > +	if (list_empty(&cdev->port_dev_list))
> > +		goto done;
> >
> >   	list_for_each_entry(pdata, &cdev->port_dev_list, node) {
> >   		if (pdata->dev)