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Date: Fri, 18 Feb 2022 19:46:07 +0300
From: Dmitry Baryshkov <dmitry.baryshkov@...aro.org>
To: Marijn Suijten <marijn.suijten@...ainline.org>,
phone-devel@...r.kernel.org, ~postmarketos/upstreaming@...ts.sr.ht,
AngeloGioacchino Del Regno
<angelogioacchino.delregno@...ainline.org>,
Konrad Dybcio <konrad.dybcio@...ainline.org>,
Martin Botka <martin.botka@...ainline.org>,
Jami Kettunen <jami.kettunen@...ainline.org>,
Pavel Dubrova <pashadubrova@...il.com>,
Rob Clark <robdclark@...il.com>, Sean Paul <sean@...rly.run>,
David Airlie <airlied@...ux.ie>,
Daniel Vetter <daniel@...ll.ch>,
Abhinav Kumar <abhinavk@...eaurora.org>,
Zhen Lei <thunder.leizhen@...wei.com>,
Bernard <bernard@...o.com>, linux-arm-msm@...r.kernel.org,
dri-devel@...ts.freedesktop.org, freedreno@...ts.freedesktop.org,
linux-kernel@...r.kernel.org
Subject: Re: [PATCH] drm/msm/dpu: Bind pingpong block to intf on active ctls
in cmd encoder
On 02/02/2022 12:48, Marijn Suijten wrote:
> On 2022-01-20 02:12:51, Dmitry Baryshkov wrote:
>> On 22/12/2021 13:55, Marijn Suijten wrote:
>>> As per the specification of DPU_CTL_ACTIVE_CFG the configuration of
>>> active blocks should be proactively specified, and the pingpong block is
>>> no different.
>>>
>>> The downstream display driver [1] confirms this by also calling
>>> bind_pingpong_blk on CTL_ACTIVE_CFG. Note that this else-if is always
>>> entered, as setup_intf_cfg - unlike this mainline dpu driver that
>>> combines both behind the same function pointer - is left NULL in favour
>>> of using setup_intf_cfg_v1 when CTL_ACTIVE_CFG is set.
>>>
>>> This solves continuous timeouts on at least the Qualcomm sm6125 SoC:
>>>
>>> [drm:dpu_encoder_frame_done_timeout:2091] [dpu error]enc31 frame done timeout
>>> [drm:_dpu_encoder_phys_cmd_handle_ppdone_timeout.isra.0] *ERROR* id:31 pp:0 kickoff timeout 0 cnt 1 koff_cnt 1
>>> [drm:dpu_encoder_phys_cmd_prepare_for_kickoff] *ERROR* failed wait_for_idle: id:31 ret:-110 pp:0
>>>
>>> In the same way this pingpong block should also be unbound followed by
>>> an interface flush when the encoder is disabled, according to the
>>> downstream display driver [2].
>>>
>>> [1]: https://source.codeaurora.org/quic/la/platform/vendor/opensource/display-drivers/tree/msm/sde/sde_encoder_phys_cmd.c?h=LA.UM.9.16.r1-08500-MANNAR.0#n167
>>> [2]: https://source.codeaurora.org/quic/la/platform/vendor/opensource/display-drivers/tree/msm/sde/sde_encoder.c?h=LA.UM.9.16.r1-08500-MANNAR.0#n2986
>>>
>>> Signed-off-by: Marijn Suijten <marijn.suijten@...ainline.org>
>>> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@...ainline.org>
>>
>> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@...aro.org>
>>
>>> ---
>>> .../drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c | 21 +++++++++++++++++++
>>> 1 file changed, 21 insertions(+)
>>>
>>> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c
>>> index 8e433af7aea4..e0e08a874f07 100644
>>> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c
>>> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c
>>> @@ -71,6 +71,13 @@ static void _dpu_encoder_phys_cmd_update_intf_cfg(
>>> intf_cfg.stream_sel = cmd_enc->stream_sel;
>>> intf_cfg.mode_3d = dpu_encoder_helper_get_3d_blend_mode(phys_enc);
>>> ctl->ops.setup_intf_cfg(ctl, &intf_cfg);
>>> +
>>> + /* setup which pp blk will connect to this intf */
>>> + if (test_bit(DPU_CTL_ACTIVE_CFG, &ctl->caps->features) && phys_enc->hw_intf->ops.bind_pingpong_blk)
>>
>> Nit: here we bind all interfaces, but later we unbind only master. Is
>> this correct?
>
> Not sure: it seems downstream only calls
> _sde/dpu_encoder_phys_cmd_update_intf_cfg when it is _not_ a ppsplit
> slave, which appears to be very similar to being the master (both check
> for ENC_ROLE_SLAVE but ppsplit also checks RM topology support for
> ppsplit). Should we do this too before calling
> _dpu_encoder_phys_cmd_update_intf_cfg?
The PP split is a special topology using a single LM, but two PP (and
two INTFs). The dpu driver doesn't provide support for it, so ppsplit is
always false.
>
> - Marijn
>
>>> + phys_enc->hw_intf->ops.bind_pingpong_blk(
>>> + phys_enc->hw_intf,
>>> + true,
>>> + phys_enc->hw_pp->idx);
>>> }
>>>
>>> static void dpu_encoder_phys_cmd_pp_tx_done_irq(void *arg, int irq_idx)
>>> @@ -507,6 +514,7 @@ static void dpu_encoder_phys_cmd_disable(struct dpu_encoder_phys *phys_enc)
>>> {
>>> struct dpu_encoder_phys_cmd *cmd_enc =
>>> to_dpu_encoder_phys_cmd(phys_enc);
>>> + struct dpu_hw_ctl *ctl;
>>>
>>> if (!phys_enc->hw_pp) {
>>> DPU_ERROR("invalid encoder\n");
>>> @@ -523,6 +531,19 @@ static void dpu_encoder_phys_cmd_disable(struct dpu_encoder_phys *phys_enc)
>>>
>>> if (phys_enc->hw_pp->ops.enable_tearcheck)
>>> phys_enc->hw_pp->ops.enable_tearcheck(phys_enc->hw_pp, false);
>>> +
>>> + if (dpu_encoder_phys_cmd_is_master(phys_enc)) {
Please remove this condition. Just check for existence of bind_pingpong_blk.
>>> + if (phys_enc->hw_intf->ops.bind_pingpong_blk) {
>>> + phys_enc->hw_intf->ops.bind_pingpong_blk(
>>> + phys_enc->hw_intf,
>>> + false,
>>> + phys_enc->hw_pp->idx);
>>> +
>>> + ctl = phys_enc->hw_ctl;
>>> + ctl->ops.update_pending_flush_intf(ctl, phys_enc->intf_idx);
>>> + }
>>> + }
>>> +
>>> phys_enc->enable_state = DPU_ENC_DISABLED;
>>> }
>>>
>>
>>
>> --
>> With best wishes
>> Dmitry
--
With best wishes
Dmitry
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