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Message-ID: <20220221133750.20297-3-alexandre.torgue@foss.st.com>
Date: Mon, 21 Feb 2022 14:37:50 +0100
From: Alexandre Torgue <alexandre.torgue@...s.st.com>
To: <arnd@...db.de>, <robh+dt@...nel.org>
CC: <linux-arm-kernel@...ts.infradead.org>,
<devicetree@...r.kernel.org>,
Alexandre Torgue <alexandre.torgue@...s.st.com>,
<linux-stm32@...md-mailman.stormreply.com>,
<linux-kernel@...r.kernel.org>, Marek Vasut <marex@...x.de>,
<jagan@...rulasolutions.com>,
Manivannan Sadhasivam <manivannan.sadhasivam@...aro.org>,
Marcin Sloniewski <marcin.sloniewski@...il.com>,
Ahmad Fatoum <a.fatoum@...gutronix.de>,
Marc Zyngier <maz@...nel.org>
Subject: [PATCH 2/2] ARM: dts: stm32: Correct masks for GIC PPI interrupts on stm32mp15
Using GIC_CPU_MASK_SIMPLE(x), x should reflect the number of CPUs.
STM32MP151 is a single A7.
STM32MP153/157 is a dual A7.
Signed-off-by: Alexandre Torgue <alexandre.torgue@...s.st.com>
diff --git a/arch/arm/boot/dts/stm32mp151.dtsi b/arch/arm/boot/dts/stm32mp151.dtsi
index 2171e7a97e92..f9aa9af31efd 100644
--- a/arch/arm/boot/dts/stm32mp151.dtsi
+++ b/arch/arm/boot/dts/stm32mp151.dtsi
@@ -45,10 +45,10 @@
timer {
compatible = "arm,armv7-timer";
- interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
- <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
- <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
- <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
+ interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>;
interrupt-parent = <&intc>;
};
diff --git a/arch/arm/boot/dts/stm32mp153.dtsi b/arch/arm/boot/dts/stm32mp153.dtsi
index 1c1889b194cf..486084e0b80b 100644
--- a/arch/arm/boot/dts/stm32mp153.dtsi
+++ b/arch/arm/boot/dts/stm32mp153.dtsi
@@ -22,6 +22,13 @@
interrupt-affinity = <&cpu0>, <&cpu1>;
};
+ timer {
+ interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
+ };
+
soc {
m_can1: can@...0e000 {
compatible = "bosch,m_can";
--
2.17.1
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