lists.openwall.net   lists  /  announce  owl-users  owl-dev  john-users  john-dev  passwdqc-users  yescrypt  popa3d-users  /  oss-security  kernel-hardening  musl  sabotage  tlsify  passwords  /  crypt-dev  xvendor  /  Bugtraq  Full-Disclosure  linux-kernel  linux-netdev  linux-ext4  linux-hardening  linux-cve-announce  PHC 
Open Source and information security mailing list archives
 
Hash Suite: Windows password security audit tool. GUI, reports in PDF.
[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]
Message-ID: <878ru442m2.wl-maz@kernel.org>
Date:   Mon, 21 Feb 2022 16:16:05 +0000
From:   Marc Zyngier <maz@...nel.org>
To:     Alexandre Torgue <alexandre.torgue@...s.st.com>
Cc:     <arnd@...db.de>, <robh+dt@...nel.org>,
        <linux-arm-kernel@...ts.infradead.org>,
        <devicetree@...r.kernel.org>,
        <linux-stm32@...md-mailman.stormreply.com>,
        <linux-kernel@...r.kernel.org>, Marek Vasut <marex@...x.de>,
        <jagan@...rulasolutions.com>,
        Manivannan Sadhasivam <manivannan.sadhasivam@...aro.org>,
        Marcin Sloniewski <marcin.sloniewski@...il.com>,
        Ahmad Fatoum <a.fatoum@...gutronix.de>
Subject: Re: [PATCH 0/2] ARM: dts: stm32: Correct masks for GIC PPI interrupts on stm32mp

On Mon, 21 Feb 2022 13:37:48 +0000,
Alexandre Torgue <alexandre.torgue@...s.st.com> wrote:
> 
> Using GIC_CPU_MASK_SIMPLE(x), x should reflect the number of CPUs.
> 
> regards
> alex
> 
> Alexandre Torgue (2):
>   ARM: dts: stm32: Correct masks for GIC PPI interrupts on stm32mp13
>   ARM: dts: stm32: Correct masks for GIC PPI interrupts on stm32mp15
> 
>  arch/arm/boot/dts/stm32mp131.dtsi | 8 ++++----
>  arch/arm/boot/dts/stm32mp151.dtsi | 8 ++++----
>  arch/arm/boot/dts/stm32mp153.dtsi | 7 +++++++
>  3 files changed, 15 insertions(+), 8 deletions(-)

FWIW:

Acked-by: Marc Zyngier <maz@...nel.org>

	M.

-- 
Without deviation from the norm, progress is not possible.

Powered by blists - more mailing lists

Powered by Openwall GNU/*/Linux Powered by OpenVZ