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Message-Id: <1645505785-2271-2-git-send-email-quic_rohiagar@quicinc.com>
Date: Tue, 22 Feb 2022 10:26:21 +0530
From: Rohit Agarwal <quic_rohiagar@...cinc.com>
To: bjorn.andersson@...aro.org, agross@...nel.org,
mturquette@...libre.com, sboyd@...nel.org, robh+dt@...nel.org,
manivannan.sadhasivam@...aro.org
Cc: linux-arm-msm@...r.kernel.org, linux-clk@...r.kernel.org,
devicetree@...r.kernel.org, linux-kernel@...r.kernel.org,
Rohit Agarwal <quic_rohiagar@...cinc.com>
Subject: [PATCH v4 1/5] dt-bindings: clock: Add A7 PLL binding for SDX65
Add information for Cortex A7 PLL clock in Qualcomm
platform SDX65.
Signed-off-by: Rohit Agarwal <quic_rohiagar@...cinc.com>
---
Documentation/devicetree/bindings/clock/qcom,a7pll.yaml | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/clock/qcom,a7pll.yaml b/Documentation/devicetree/bindings/clock/qcom,a7pll.yaml
index 8666e99..0e96f69 100644
--- a/Documentation/devicetree/bindings/clock/qcom,a7pll.yaml
+++ b/Documentation/devicetree/bindings/clock/qcom,a7pll.yaml
@@ -10,7 +10,7 @@ maintainers:
- Manivannan Sadhasivam <manivannan.sadhasivam@...aro.org>
description:
- The A7 PLL on the Qualcomm platforms like SDX55 is used to provide high
+ The A7 PLL on the Qualcomm platforms like SDX55, SDX65 is used to provide high
frequency clock to the CPU.
properties:
--
2.7.4
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