linux-kernel - Re: [PATCH 0/4] spi-mem: Allow specifying the byte order in DTR mode

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Date:   Tue, 22 Feb 2022 13:54:56 +0000
From:   <Tudor.Ambarus@...rochip.com>
To:     <michael@...le.cc>
CC:     <p.yadav@...com>, <broonie@...nel.org>,
        <miquel.raynal@...tlin.com>, <richard@....at>, <vigneshr@...com>,
        <linux-mtd@...ts.infradead.org>, <linux-kernel@...r.kernel.org>,
        <linux-spi@...r.kernel.org>, <Nicolas.Ferre@...rochip.com>,
        <zhengxunli@...c.com.tw>, <jaimeliao@...c.com.tw>
Subject: Re: [PATCH 0/4] spi-mem: Allow specifying the byte order in DTR mode

On 2/21/22 09:44, Michael Walle wrote:
> EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
> 
> Am 2022-02-18 15:58, schrieb Tudor Ambarus:
>> Fortunately there are controllers
>> that can swap back the bytes at runtime, fixing the endiannesses.
>> Provide
>> a way for the upper layers to specify the byte order in DTR mode.
> 
> Are there any patches for the atmel-quadspi yet? What happens if

not public, but will publish them these days.

> the controller doesn't support it? Will there be a software fallback?

no need for a fallback, the controller can ignore op->data.dtr_bswap16 if
it can't swap bytes.

Here's the changes that enable this on atmel-quadspi:

Author: Tudor Ambarus <tudor.ambarus@...rochip.com>
Date:   Thu Feb 17 10:48:10 2022 +0200

    spi: atmel-quadspi: Set endianness on 8D-8D-8D mode according to the flash requirements
    
    Macronix swaps bytes on a 16-bit boundary when configured in Octal DTR.
    The byte order of 16-bit words is swapped when read or write written in
    8D-8D-8D mode compared to STR modes. Set the endianness flash requirements
    to avoid endianness problems during boot stages.
    
    Signed-off-by: Tudor Ambarus <tudor.ambarus@...rochip.com>

diff --git a/drivers/spi/atmel-quadspi.c b/drivers/spi/atmel-quadspi.c
index a4ba94ce84f1..c4a3963f7c84 100644
--- a/drivers/spi/atmel-quadspi.c
+++ b/drivers/spi/atmel-quadspi.c
@@ -697,6 +697,8 @@ static int atmel_qspi_sama7g5_set_cfg(struct atmel_qspi *aq,
                ifr |= QSPI_IFR_DDREN;
                if (op->cmd.dtr)
                        ifr |= QSPI_IFR_DDRCMDEN;
+               if (op->data.dtr_bswap16)
+                       ifr |= QSPI_IFR_END;
 
                ifr |= QSPI_IFR_DQSEN;
        }