[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]
Message-ID: <YhfZcJEmHq432DX4@robh.at.kernel.org>
Date: Thu, 24 Feb 2022 13:16:00 -0600
From: Rob Herring <robh@...nel.org>
To: Rohit Agarwal <quic_rohiagar@...cinc.com>
Cc: manivannan.sadhasivam@...aro.org, sboyd@...nel.org,
robh+dt@...nel.org, agross@...nel.org, mturquette@...libre.com,
linux-clk@...r.kernel.org, bjorn.andersson@...aro.org,
linux-arm-msm@...r.kernel.org, devicetree@...r.kernel.org,
linux-kernel@...r.kernel.org
Subject: Re: [PATCH v4 1/5] dt-bindings: clock: Add A7 PLL binding for SDX65
On Tue, 22 Feb 2022 10:26:21 +0530, Rohit Agarwal wrote:
> Add information for Cortex A7 PLL clock in Qualcomm
> platform SDX65.
>
> Signed-off-by: Rohit Agarwal <quic_rohiagar@...cinc.com>
> ---
> Documentation/devicetree/bindings/clock/qcom,a7pll.yaml | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
Acked-by: Rob Herring <robh@...nel.org>
Powered by blists - more mailing lists