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Message-Id: <20220224235458.74BD4C340F1@smtp.kernel.org>
Date: Thu, 24 Feb 2022 15:54:56 -0800
From: Stephen Boyd <sboyd@...nel.org>
To: Rohit Agarwal <quic_rohiagar@...cinc.com>, agross@...nel.org,
bjorn.andersson@...aro.org, manivannan.sadhasivam@...aro.org,
mturquette@...libre.com, robh+dt@...nel.org
Cc: linux-arm-msm@...r.kernel.org, linux-clk@...r.kernel.org,
devicetree@...r.kernel.org, linux-kernel@...r.kernel.org,
Rohit Agarwal <quic_rohiagar@...cinc.com>
Subject: Re: [PATCH v4 1/5] dt-bindings: clock: Add A7 PLL binding for SDX65
Quoting Rohit Agarwal (2022-02-21 20:56:21)
> Add information for Cortex A7 PLL clock in Qualcomm
> platform SDX65.
>
> Signed-off-by: Rohit Agarwal <quic_rohiagar@...cinc.com>
> ---
Reviewed-by: Stephen Boyd <sboyd@...nel.org>
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