linux-kernel - Re: [PATCH] KVM: x86/pmu: Fix reserved bits for AMD PerfEvtSeln register

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Message-ID: <CALMp9eSWJevnn3vs5==9ay5vRL_djfq28bawUEP3KzBft3FOrg@mail.gmail.com>
Date:   Fri, 25 Feb 2022 14:26:58 -0800
From:   Jim Mattson <jmattson@...gle.com>
To:     Like Xu <like.xu.linux@...il.com>
Cc:     David Dunn <daviddunn@...gle.com>,
        Paolo Bonzini <pbonzini@...hat.com>,
        Joerg Roedel <joro@...tes.org>,
        Kim Phillips <kim.phillips@....com>,
        Maxim Levitsky <mlevitsk@...hat.com>,
        Sean Christopherson <seanjc@...gle.com>,
        Vitaly Kuznetsov <vkuznets@...hat.com>,
        Wanpeng Li <wanpengli@...cent.com>, kvm@...r.kernel.org,
        linux-kernel@...r.kernel.org, Lotus Fenn <lotusf@...gle.com>
Subject: Re: [PATCH] KVM: x86/pmu: Fix reserved bits for AMD PerfEvtSeln register

On Tue, Feb 15, 2022 at 11:47 PM Like Xu <like.xu.linux@...il.com> wrote:
>
> On 12/2/2022 4:39 pm, Jim Mattson wrote:
> >> -       pmu->reserved_bits = 0xffffffff00200000ull;
> >> +       pmu->reserved_bits = 0xfffffff000280000ull;
> > Bits 40 and 41 are guest mode and host mode. They cannot be reserved
> > if the guest supports nested SVM.
> >
>
> Indeed, we need (some hands) to do more pmu tests on nested SVM.

Actually, it's not just nested SVM.

When we enable vPMU for an Ubuntu guest that is incapable of nested
SVM, we see errors like the following:

root@...ntu1804:~# perf stat -e r26 -a sleep 1

 Performance counter stats for 'system wide':

                 0      r26


       1.001070977 seconds time elapsed

Feb 23 03:59:58 Ubuntu1804 kernel: [  405.379957] unchecked MSR access
error: WRMSR to 0xc0010200 (tried to write 0x0000020000130026) at rIP:
0xffffffff9b276a28 (native_write_msr+0x8/0x30)
Feb 23 03:59:58 Ubuntu1804 kernel: [  405.379958] Call Trace:
Feb 23 03:59:58 Ubuntu1804 kernel: [  405.379963]
amd_pmu_disable_event+0x27/0x90

If the standard Linux perf tool sets "exclude_guest" by default, even
when EFER.SVME is clear, then amd_core_hw_config() in the guest kernel
will set bit 41 (again, without checking EFER.SVME). This WRMSR should
not raise #GP.

Current AMD hardware doesn't raise #GP for any value written to a
PerfEvtSeln MSR. I don't think KVM should ever synthesize a #GP
either. Perhaps we should just mask off the bits that you have
indicated as reserved, above.