linux-kernel - RE: [PATCH] dt-bindings: serial: fsl-lpuart: Add imx93 compatible string

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives

Hash Suite for Android: free password hash cracker in your pocket

[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]

Date:   Mon, 28 Feb 2022 00:44:46 +0000
From:   Peng Fan <peng.fan@....com>
To:     Rob Herring <robh@...nel.org>,
        "Peng Fan (OSS)" <peng.fan@....nxp.com>
CC:     "gregkh@...uxfoundation.org" <gregkh@...uxfoundation.org>,
        "linux-serial@...r.kernel.org" <linux-serial@...r.kernel.org>,
        "devicetree@...r.kernel.org" <devicetree@...r.kernel.org>,
        "linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>
Subject: RE: [PATCH] dt-bindings: serial: fsl-lpuart: Add imx93 compatible
 string

Hi Rob,

> Subject: Re: [PATCH] dt-bindings: serial: fsl-lpuart: Add imx93 compatible
> string
> 
> On Tue, Feb 15, 2022 at 04:13:34PM +0800, Peng Fan (OSS) wrote:
> > From: Peng Fan <peng.fan@....com>
> >
> > The lpuart on i.MX93 is derived from i.MX8ULP with some industrial
> > enhancements, it uses three compatible strings, so update the
> 
> Looks like it's 2 compatible strings...

Oh, yes. i.MX8ULP/7ULP is same uart IP.

> 
> > compatible string for i.MX93. But for a few instants,
> 
> s/instants/instances/
> 
> > DTR_B, DSR_B, DCD_B and RIN_B pins are supported, so use one
> > compatible string fsl,imx93-lpuart-v2
> 
> If the differences are just what gets pinned out, then I think the differences
> should be handled with separate properties. We probably already have some.
> 
> Plus, while you may have all the above signals, a board design may still only
> use a subset.

It is SoC integration level with above features not support in some instances,
so no such signals connected to SoC pin.

Saying LPUART IP itself support DTR/DSR/DCD/RIN, but instance A has the
feature disabled when doing SoC integration, instance B has the feature enabled
when doing SoC integration. What's your suggestion with such case?

Thanks,
Peng.

> 
> >
> > Signed-off-by: Peng Fan <peng.fan@....com>
> > ---
> >  Documentation/devicetree/bindings/serial/fsl-lpuart.yaml | 2 ++
> >  1 file changed, 2 insertions(+)
> >
> > diff --git a/Documentation/devicetree/bindings/serial/fsl-lpuart.yaml
> > b/Documentation/devicetree/bindings/serial/fsl-lpuart.yaml
> > index 6e04e3848261..d7805f31ccc2 100644
> > --- a/Documentation/devicetree/bindings/serial/fsl-lpuart.yaml
> > +++ b/Documentation/devicetree/bindings/serial/fsl-lpuart.yaml
> > @@ -24,6 +24,8 @@ properties:
> >            - fsl,imxrt1050-lpuart
> >        - items:
> >            - enum:
> > +              - fsl,imx93-lpuart
> > +              - fsl,imx93-lpuart-v2
> >                - fsl,imx8qxp-lpuart
> >                - fsl,imx8ulp-lpuart
> >            - const: fsl,imx7ulp-lpuart
> > --
> > 2.25.1
> >
> >