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Message-ID: <39ce4a12-ff56-e0cf-b0b2-2a3545a9cb7f@canonical.com>
Date: Mon, 28 Feb 2022 10:20:39 +0100
From: Krzysztof Kozlowski <krzysztof.kozlowski@...onical.com>
To: qinjian[覃健] <qinjian@...lus1.com>,
"robh+dt@...nel.org" <robh+dt@...nel.org>
Cc: "mturquette@...libre.com" <mturquette@...libre.com>,
"sboyd@...nel.org" <sboyd@...nel.org>,
"tglx@...utronix.de" <tglx@...utronix.de>,
"maz@...nel.org" <maz@...nel.org>,
"p.zabel@...gutronix.de" <p.zabel@...gutronix.de>,
"linux@...linux.org.uk" <linux@...linux.org.uk>,
"broonie@...nel.org" <broonie@...nel.org>,
"arnd@...db.de" <arnd@...db.de>,
"stefan.wahren@...e.com" <stefan.wahren@...e.com>,
"linux-arm-kernel@...ts.infradead.org"
<linux-arm-kernel@...ts.infradead.org>,
"devicetree@...r.kernel.org" <devicetree@...r.kernel.org>,
"linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
"linux-clk@...r.kernel.org" <linux-clk@...r.kernel.org>,
Wells Lu 呂芳騰 <wells.lu@...plus.com>,
Rob Herring <robh@...nel.org>
Subject: Re: [PATCH v9 05/10] dt-bindings: clock: Add bindings for SP7021
clock driver
On 28/02/2022 07:31, qinjian[覃健] wrote:
>>> +examples:
>>> + - |
>>> + clkc: clock-controller@...00000 {
>>> + compatible = "sunplus,sp7021-clkc";
>>> + #clock-cells = <1>;
>>> + reg = <0x9c000000 0x280>;
>>> + clocks = <&extclk>, <&clkc PLL_SYS>;
>>
>> Except the warning pointed out by Rob's bot, it looks like you feed this
>> clock-controller with a clock from itself. Is there a point to express
>> it in DTS at all?
>
> Yes, pllsys is an internal clock, but it also as a parent clock for some other
> clocks in this clock-controller.
What is the point to express it in DTS? Usually such internal
parent-child relation is described in the driver.
And how does it even work? How can you get a clock from a device before
you registered that device?
Best regards,
Krzysztof
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