linux-kernel - Re: [2/4] dt-bindings: reset: mt8186: add toprgu reset-controller header file

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Date:   Tue, 1 Mar 2022 10:56:19 +0800
From:   Rex-BC Chen <rex-bc.chen@...iatek.com>
To:     Guenter Roeck <linux@...ck-us.net>, <wim@...ux-watchdog.org>,
        <matthias.bgg@...il.com>, <robh+dt@...nel.org>,
        <p.zabel@...gutronix.de>
CC:     <runyang.chen@...iatek.com>, <linux-watchdog@...r.kernel.org>,
        <devicetree@...r.kernel.org>,
        <linux-arm-kernel@...ts.infradead.org>,
        <linux-mediatek@...ts.infradead.org>,
        <linux-kernel@...r.kernel.org>,
        <Project_Global_Chrome_Upstream_Group@...iatek.com>
Subject: Re: [2/4] dt-bindings: reset: mt8186: add toprgu reset-controller
 header file

Hello Guenter,

Thanks for your review.
I will do this in next version.

BRs,
Rex

On Fri, 2022-02-25 at 08:37 -0800, Guenter Roeck wrote:
> On 2/15/22 17:45, Rex-BC Chen wrote:
> > From: Runyang Chen <runyang.chen@...iatek.com>
> > 
> > Add toprgu reset-controller header file for MT8186.
> > 
> > Signed-off-by: Runyang Chen <runyang.chen@...iatek.com>
> > Signed-off-by: Rex-BC Chen <rex-bc.chen@...iatek.com>
> 
> With the next patch squashed into this one:
> 
> Reviewed-by: Guenter Roeck <linux@...ck-us.net>
> 
> > ---
> >   include/dt-bindings/reset/mt8186-resets.h | 33
> > +++++++++++++++++++++++
> >   1 file changed, 33 insertions(+)
> >   create mode 100644 include/dt-bindings/reset/mt8186-resets.h
> > 
> > diff --git a/include/dt-bindings/reset/mt8186-resets.h
> > b/include/dt-bindings/reset/mt8186-resets.h
> > new file mode 100644
> > index 000000000000..36e5764e2e6c
> > --- /dev/null
> > +++ b/include/dt-bindings/reset/mt8186-resets.h
> > @@ -0,0 +1,33 @@
> > +/* SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) */
> > +/*
> > + * Copyright (c) 2022 MediaTek Inc.
> > + * Author: Runyang Chen <runyang.chen@...iatek.com>
> > + */
> > +
> > +#ifndef _DT_BINDINGS_RESET_CONTROLLER_MT8186
> > +#define _DT_BINDINGS_RESET_CONTROLLER_MT8186
> > +
> > +#define MT8186_TOPRGU_INFRA_SW_RST				0
> > +#define MT8186_TOPRGU_MM_SW_RST					
> > 1
> > +#define MT8186_TOPRGU_MFG_SW_RST				2
> > +#define MT8186_TOPRGU_VENC_SW_RST				3
> > +#define MT8186_TOPRGU_VDEC_SW_RST				4
> > +#define MT8186_TOPRGU_IMG_SW_RST				5
> > +#define MT8186_TOPRGU_DDR_SW_RST				6
> > +#define MT8186_TOPRGU_INFRA_AO_SW_RST				
> > 8
> > +#define MT8186_TOPRGU_CONNSYS_SW_RST				
> > 9
> > +#define MT8186_TOPRGU_APMIXED_SW_RST				
> > 10
> > +#define MT8186_TOPRGU_PWRAP_SW_RST				11
> > +#define MT8186_TOPRGU_CONN_MCU_SW_RST				
> > 12
> > +#define MT8186_TOPRGU_IPNNA_SW_RST				13
> > +#define MT8186_TOPRGU_WPE_SW_RST				14
> > +#define MT8186_TOPRGU_ADSP_SW_RST				15
> > +#define MT8186_TOPRGU_AUDIO_SW_RST				17
> > +#define MT8186_TOPRGU_CAM_MAIN_SW_RST				
> > 18
> > +#define MT8186_TOPRGU_CAM_RAWA_SW_RST				
> > 19
> > +#define MT8186_TOPRGU_CAM_RAWB_SW_RST				
> > 20
> > +#define MT8186_TOPRGU_IPE_SW_RST				21
> > +#define MT8186_TOPRGU_IMG2_SW_RST				22
> > +#define MT8186_TOPRGU_SW_RST_NUM				23
> > +
> > +#endif  /* _DT_BINDINGS_RESET_CONTROLLER_MT8186 */
> 
>