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Date: Tue, 1 Mar 2022 17:35:00 -0600
From: Rob Herring <robh@...nel.org>
To: Mauro Carvalho Chehab <mchehab@...nel.org>,
Krzysztof Kozlowski <krzysztof.kozlowski@...onical.com>,
Matthias Brugger <matthias.bgg@...il.com>,
Yunfei Dong <yunfei.dong@...iatek.com>
Cc: linux-media@...r.kernel.org, devicetree@...r.kernel.org,
linux-kernel@...r.kernel.org, linux-arm-kernel@...ts.infradead.org,
linux-mediatek@...ts.infradead.org
Subject: [PATCH] dt-bindings: media: mediatek,vcodec: Fix addressing cell sizes
'dma-ranges' in the example is written for cell sizes of 2 cells, but
the schema and example specify sizes of 1 cell. As the h/w has a bus
address of >32-bits, cell sizes of 2 is correct. Update the schema's
'#address-cells' and '#size-cells' to be 2 and adjust the example
throughout.
There's no error currently because dtc only checks 'dma-ranges' is a
correct multiple number of cells (3) and the schema checking is based on
bracketing of entries.
Signed-off-by: Rob Herring <robh@...nel.org>
---
I noticed the driver is checking 'dma-ranges' itself. That's generally
wrong as the core code should be configuring bus dma masks
automatically.
---
.../media/mediatek,vcodec-subdev-decoder.yaml | 122 +++++++++---------
1 file changed, 64 insertions(+), 58 deletions(-)
diff --git a/Documentation/devicetree/bindings/media/mediatek,vcodec-subdev-decoder.yaml b/Documentation/devicetree/bindings/media/mediatek,vcodec-subdev-decoder.yaml
index d587fc3e39fb..7687be0f50aa 100644
--- a/Documentation/devicetree/bindings/media/mediatek,vcodec-subdev-decoder.yaml
+++ b/Documentation/devicetree/bindings/media/mediatek,vcodec-subdev-decoder.yaml
@@ -72,10 +72,10 @@ properties:
Describes the physical address space of IOMMU maps to memory.
"#address-cells":
- const: 1
+ const: 2
"#size-cells":
- const: 1
+ const: 2
ranges: true
@@ -205,61 +205,67 @@ examples:
#include <dt-bindings/clock/mt8192-clk.h>
#include <dt-bindings/power/mt8192-power.h>
- video-codec@...00000 {
- compatible = "mediatek,mt8192-vcodec-dec";
- mediatek,scp = <&scp>;
- iommus = <&iommu0 M4U_PORT_L4_VDEC_MC_EXT>;
- dma-ranges = <0x1 0x0 0x0 0x40000000 0x0 0xfff00000>;
- #address-cells = <1>;
- #size-cells = <1>;
- ranges = <0 0x16000000 0x40000>;
- reg = <0x16000000 0x1000>; /* VDEC_SYS */
- vcodec-lat@...00 {
- compatible = "mediatek,mtk-vcodec-lat";
- reg = <0x10000 0x800>;
- interrupts = <GIC_SPI 426 IRQ_TYPE_LEVEL_HIGH 0>;
- iommus = <&iommu0 M4U_PORT_L5_VDEC_LAT0_VLD_EXT>,
- <&iommu0 M4U_PORT_L5_VDEC_LAT0_VLD2_EXT>,
- <&iommu0 M4U_PORT_L5_VDEC_LAT0_AVC_MV_EXT>,
- <&iommu0 M4U_PORT_L5_VDEC_LAT0_PRED_RD_EXT>,
- <&iommu0 M4U_PORT_L5_VDEC_LAT0_TILE_EXT>,
- <&iommu0 M4U_PORT_L5_VDEC_LAT0_WDMA_EXT>,
- <&iommu0 M4U_PORT_L5_VDEC_LAT0_RG_CTRL_DMA_EXT>,
- <&iommu0 M4U_PORT_L5_VDEC_UFO_ENC_EXT>;
- clocks = <&topckgen CLK_TOP_VDEC_SEL>,
- <&vdecsys_soc CLK_VDEC_SOC_VDEC>,
- <&vdecsys_soc CLK_VDEC_SOC_LAT>,
- <&vdecsys_soc CLK_VDEC_SOC_LARB1>,
- <&topckgen CLK_TOP_MAINPLL_D4>;
- clock-names = "sel", "soc-vdec", "soc-lat", "vdec", "top";
- assigned-clocks = <&topckgen CLK_TOP_VDEC_SEL>;
- assigned-clock-parents = <&topckgen CLK_TOP_MAINPLL_D4>;
- power-domains = <&spm MT8192_POWER_DOMAIN_VDEC>;
- };
-
- vcodec-core@...00 {
- compatible = "mediatek,mtk-vcodec-core";
- reg = <0x25000 0x1000>;
- interrupts = <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH 0>;
- iommus = <&iommu0 M4U_PORT_L4_VDEC_MC_EXT>,
- <&iommu0 M4U_PORT_L4_VDEC_UFO_EXT>,
- <&iommu0 M4U_PORT_L4_VDEC_PP_EXT>,
- <&iommu0 M4U_PORT_L4_VDEC_PRED_RD_EXT>,
- <&iommu0 M4U_PORT_L4_VDEC_PRED_WR_EXT>,
- <&iommu0 M4U_PORT_L4_VDEC_PPWRAP_EXT>,
- <&iommu0 M4U_PORT_L4_VDEC_TILE_EXT>,
- <&iommu0 M4U_PORT_L4_VDEC_VLD_EXT>,
- <&iommu0 M4U_PORT_L4_VDEC_VLD2_EXT>,
- <&iommu0 M4U_PORT_L4_VDEC_AVC_MV_EXT>,
- <&iommu0 M4U_PORT_L4_VDEC_RG_CTRL_DMA_EXT>;
- clocks = <&topckgen CLK_TOP_VDEC_SEL>,
- <&vdecsys CLK_VDEC_VDEC>,
- <&vdecsys CLK_VDEC_LAT>,
- <&vdecsys CLK_VDEC_LARB1>,
- <&topckgen CLK_TOP_MAINPLL_D4>;
- clock-names = "sel", "soc-vdec", "soc-lat", "vdec", "top";
- assigned-clocks = <&topckgen CLK_TOP_VDEC_SEL>;
- assigned-clock-parents = <&topckgen CLK_TOP_MAINPLL_D4>;
- power-domains = <&spm MT8192_POWER_DOMAIN_VDEC2>;
+ bus@...00000 {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges = <0 0x16000000 0x16000000 0 0x40000>;
+
+ video-codec@...00000 {
+ compatible = "mediatek,mt8192-vcodec-dec";
+ mediatek,scp = <&scp>;
+ iommus = <&iommu0 M4U_PORT_L4_VDEC_MC_EXT>;
+ dma-ranges = <0x1 0x0 0x0 0x40000000 0x0 0xfff00000>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges = <0 0 0 0x16000000 0 0x40000>;
+ reg = <0 0x16000000 0 0x1000>; /* VDEC_SYS */
+ vcodec-lat@...00 {
+ compatible = "mediatek,mtk-vcodec-lat";
+ reg = <0 0x10000 0 0x800>;
+ interrupts = <GIC_SPI 426 IRQ_TYPE_LEVEL_HIGH 0>;
+ iommus = <&iommu0 M4U_PORT_L5_VDEC_LAT0_VLD_EXT>,
+ <&iommu0 M4U_PORT_L5_VDEC_LAT0_VLD2_EXT>,
+ <&iommu0 M4U_PORT_L5_VDEC_LAT0_AVC_MV_EXT>,
+ <&iommu0 M4U_PORT_L5_VDEC_LAT0_PRED_RD_EXT>,
+ <&iommu0 M4U_PORT_L5_VDEC_LAT0_TILE_EXT>,
+ <&iommu0 M4U_PORT_L5_VDEC_LAT0_WDMA_EXT>,
+ <&iommu0 M4U_PORT_L5_VDEC_LAT0_RG_CTRL_DMA_EXT>,
+ <&iommu0 M4U_PORT_L5_VDEC_UFO_ENC_EXT>;
+ clocks = <&topckgen CLK_TOP_VDEC_SEL>,
+ <&vdecsys_soc CLK_VDEC_SOC_VDEC>,
+ <&vdecsys_soc CLK_VDEC_SOC_LAT>,
+ <&vdecsys_soc CLK_VDEC_SOC_LARB1>,
+ <&topckgen CLK_TOP_MAINPLL_D4>;
+ clock-names = "sel", "soc-vdec", "soc-lat", "vdec", "top";
+ assigned-clocks = <&topckgen CLK_TOP_VDEC_SEL>;
+ assigned-clock-parents = <&topckgen CLK_TOP_MAINPLL_D4>;
+ power-domains = <&spm MT8192_POWER_DOMAIN_VDEC>;
+ };
+
+ vcodec-core@...00 {
+ compatible = "mediatek,mtk-vcodec-core";
+ reg = <0 0x25000 0 0x1000>;
+ interrupts = <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH 0>;
+ iommus = <&iommu0 M4U_PORT_L4_VDEC_MC_EXT>,
+ <&iommu0 M4U_PORT_L4_VDEC_UFO_EXT>,
+ <&iommu0 M4U_PORT_L4_VDEC_PP_EXT>,
+ <&iommu0 M4U_PORT_L4_VDEC_PRED_RD_EXT>,
+ <&iommu0 M4U_PORT_L4_VDEC_PRED_WR_EXT>,
+ <&iommu0 M4U_PORT_L4_VDEC_PPWRAP_EXT>,
+ <&iommu0 M4U_PORT_L4_VDEC_TILE_EXT>,
+ <&iommu0 M4U_PORT_L4_VDEC_VLD_EXT>,
+ <&iommu0 M4U_PORT_L4_VDEC_VLD2_EXT>,
+ <&iommu0 M4U_PORT_L4_VDEC_AVC_MV_EXT>,
+ <&iommu0 M4U_PORT_L4_VDEC_RG_CTRL_DMA_EXT>;
+ clocks = <&topckgen CLK_TOP_VDEC_SEL>,
+ <&vdecsys CLK_VDEC_VDEC>,
+ <&vdecsys CLK_VDEC_LAT>,
+ <&vdecsys CLK_VDEC_LARB1>,
+ <&topckgen CLK_TOP_MAINPLL_D4>;
+ clock-names = "sel", "soc-vdec", "soc-lat", "vdec", "top";
+ assigned-clocks = <&topckgen CLK_TOP_VDEC_SEL>;
+ assigned-clock-parents = <&topckgen CLK_TOP_MAINPLL_D4>;
+ power-domains = <&spm MT8192_POWER_DOMAIN_VDEC2>;
+ };
};
};
--
2.32.0
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