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Message-ID: <20220304074846.bkzwn4c3voaxxqzu@pengutronix.de>
Date: Fri, 4 Mar 2022 08:48:46 +0100
From: Uwe Kleine-König <u.kleine-koenig@...gutronix.de>
To: Sean Anderson <sean.anderson@...o.com>
Cc: linux-pwm@...r.kernel.org, devicetree@...r.kernel.org,
Thierry Reding <thierry.reding@...il.com>,
linux-kernel@...r.kernel.org, Lee Jones <lee.jones@...aro.org>,
Mubin Usman Sayyed <MUBINUSM@...inx.com>,
linux-arm-kernel@...ts.infradead.org, michal.simek@...inx.com,
Alvaro Gamez <alvaro.gamez@...ent.com>
Subject: Re: [PATCH v14 2/2] pwm: Add support for Xilinx AXI Timer
Hello,
On Thu, Mar 03, 2022 at 05:35:43PM -0500, Sean Anderson wrote:
> This adds PWM support for Xilinx LogiCORE IP AXI soft timers commonly
> found on Xilinx FPGAs. At the moment clock control is very basic: we
> just enable the clock during probe and pin the frequency. In the future,
> someone could add support for disabling the clock when not in use.
>
> Some common code has been specially demarcated. While currently only
> used by the PWM driver, it is anticipated that it may be split off in
> the future to be used by the timer driver as well.
>
> This driver was written with reference to Xilinx DS764 for v1.03.a [1].
>
> [1] https://www.xilinx.com/support/documentation/ip_documentation/axi_timer/v1_03_a/axi_timer_ds764.pdf
>
> Signed-off-by: Sean Anderson <sean.anderson@...o.com>
> Acked-by: Michal Simek <michal.simek@...inx.com>
One little thing below. Not worth respinning for just that though, so:
Reviewed-by: Uwe Kleine-König <u.kleine-koenig@...gutronix.de>
> + /*
> + * 100% duty cycle results in constant low output. This may be (very)
> + * wrong if rate >= 1 GHz, so fix this if you have such hardware :)
> + */
In v13 I asked for s/>= 1GHz/> 1 GHz/. You seem to have missed, that
this contains two suggested changes. So there is s/>=/>/ left.
Best regards
Uwe
--
Pengutronix e.K. | Uwe Kleine-König |
Industrial Linux Solutions | https://www.pengutronix.de/ |
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