linux-kernel - Re: [PATCH v14 1/2] dt-bindings: pwm: Add Xilinx AXI Timer

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives

Hash Suite: Windows password security audit tool. GUI, reports in PDF.

[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]

Message-ID: <YmLXyoBOPA8NqjHY@orome>
Date:   Fri, 22 Apr 2022 18:28:58 +0200
From:   Thierry Reding <thierry.reding@...il.com>
To:     Sean Anderson <sean.anderson@...o.com>
Cc:     linux-pwm@...r.kernel.org, devicetree@...r.kernel.org,
        linux-kernel@...r.kernel.org, Lee Jones <lee.jones@...aro.org>,
        Mubin Usman Sayyed <MUBINUSM@...inx.com>,
        linux-arm-kernel@...ts.infradead.org,
        Uwe Kleine-König 
        <u.kleine-koenig@...gutronix.de>, michal.simek@...inx.com,
        Alvaro Gamez <alvaro.gamez@...ent.com>,
        Rob Herring <robh@...nel.org>
Subject: Re: [PATCH v14 1/2] dt-bindings: pwm: Add Xilinx AXI Timer

On Thu, Mar 03, 2022 at 05:35:42PM -0500, Sean Anderson wrote:
> This adds a binding for the Xilinx LogiCORE IP AXI Timer. This device is a
> "soft" block, so it has some parameters which would not be configurable in
> most hardware. This binding is usually automatically generated by Xilinx's
> tools, so the names and values of some properties should be kept as they
> are, if possible. In addition, this binding is already in the kernel at
> arch/microblaze/boot/dts/system.dts, and in user software such as QEMU.
> 
> The existing driver uses the clock-frequency property, or alternatively the
> /cpus/timebase-frequency property as its frequency input. Because these
> properties are deprecated, they have not been included with this schema.
> All new bindings should use the clocks/clock-names properties to specify
> the parent clock.
> 
> Because we need to init timer devices so early in boot, we determine if we
> should use the PWM driver or the clocksource/clockevent driver by the
> presence/absence, respectively, of #pwm-cells. Because both counters are
> used by the PWM, there is no need for a separate property specifying which
> counters are to be used for the PWM.
> 
> Signed-off-by: Sean Anderson <sean.anderson@...o.com>
> Reviewed-by: Rob Herring <robh@...nel.org>
> ---
> 
> (no changes since v8)
> 
> Changes in v8:
> - Set additionalProperties: false
> 
> Changes in v7:
> - Add #pwm-cells to properties
> - Document why additionalProperties is true
> 
> Changes in v6:
> - Enumerate possible counter widths
> - Fix incorrect schema id
> 
> Changes in v5:
> - Add example for timer binding
> - Fix indentation lint
> - Move schema into the timer directory
> - Remove xlnx,axi-timer-2.0 compatible string
> - Update commit message to reflect revisions
> 
> Changes in v4:
> - Make some properties optional for clocksource drivers
> - Predicate PWM driver on the presence of #pwm-cells
> - Remove references to generate polarity so this can get merged
> 
> Changes in v3:
> - Add an example with non-deprecated properties only.
> - Add xlnx,pwm and xlnx,gen?-active-low properties.
> - Make newer replacement properties mutually-exclusive with what they
>   replace
> - Mark all boolean-as-int properties as deprecated
> 
> Changes in v2:
> - Use 32-bit addresses for example binding
> 
>  .../bindings/timer/xlnx,xps-timer.yaml        | 92 +++++++++++++++++++
>  1 file changed, 92 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/timer/xlnx,xps-timer.yaml

Applied, thanks.

Thierry

Download attachment "signature.asc" of type "application/pgp-signature" (834 bytes)