linux-kernel - Re: [PATCH 1/2] hwrng: mpfs - add polarfire soc hwrng support

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Message-ID: <YicMBhn81HmtJMiF@owl.dominikbrodowski.net>
Date:   Tue, 8 Mar 2022 08:55:50 +0100
From:   Dominik Brodowski <linux@...inikbrodowski.net>
To:     conor.dooley@...rochip.com
Cc:     mpm@...enic.com, herbert@...dor.apana.org.au,
        lewis.hanly@...rochip.com, linux-kernel@...r.kernel.org,
        linux-crypto@...r.kernel.org, linux-riscv@...ts.infradead.org
Subject: Re: [PATCH 1/2] hwrng: mpfs - add polarfire soc hwrng support

Am Mon, Mar 07, 2022 at 03:40:23PM +0000 schrieb conor.dooley@...rochip.com:
> From: Conor Dooley <conor.dooley@...rochip.com>
> 
> Add a driver to access the hardware random number generator on the
> Polarfire SoC. The hwrng can only be accessed via the system controller,
> so use the mailbox interface the system controller exposes to access the
> hwrng.
> 
> Signed-off-by: Conor Dooley <conor.dooley@...rochip.com>
> ---
>  drivers/char/hw_random/Kconfig    |  13 ++++
>  drivers/char/hw_random/Makefile   |   1 +
>  drivers/char/hw_random/mpfs-rng.c | 103 ++++++++++++++++++++++++++++++
>  3 files changed, 117 insertions(+)
>  create mode 100644 drivers/char/hw_random/mpfs-rng.c
> 
> diff --git a/drivers/char/hw_random/Kconfig b/drivers/char/hw_random/Kconfig
> index 9704963f9d50..69f1fd538589 100644
> --- a/drivers/char/hw_random/Kconfig
> +++ b/drivers/char/hw_random/Kconfig
> @@ -385,6 +385,19 @@ config HW_RANDOM_PIC32
>  
>  	  If unsure, say Y.
>  
> +config HW_RANDOM_POLARFIRE_SOC
> +	tristate "Microchip PolarFire SoC Random Number Generator support"
> +	depends on HW_RANDOM && POLARFIRE_SOC_SYS_CTRL
> +	help
> +	  This driver provides kernel-side support for the Random Number
> +	  Generator hardware found on PolarFire SoC (MPFS).
> +
> +	  To compile this driver as a module, choose M here. The
> +	  module will be called mfps_rng.
> +
> +	  If unsure, say N.
> +
> +
>  config HW_RANDOM_MESON
>  	tristate "Amlogic Meson Random Number Generator support"
>  	depends on HW_RANDOM
> diff --git a/drivers/char/hw_random/Makefile b/drivers/char/hw_random/Makefile
> index 584d47ba32f7..3e948cf04476 100644
> --- a/drivers/char/hw_random/Makefile
> +++ b/drivers/char/hw_random/Makefile
> @@ -46,3 +46,4 @@ obj-$(CONFIG_HW_RANDOM_CCTRNG) += cctrng.o
>  obj-$(CONFIG_HW_RANDOM_XIPHERA) += xiphera-trng.o
>  obj-$(CONFIG_HW_RANDOM_ARM_SMCCC_TRNG) += arm_smccc_trng.o
>  obj-$(CONFIG_HW_RANDOM_CN10K) += cn10k-rng.o
> +obj-$(CONFIG_HW_RANDOM_POLARFIRE_SOC) += mpfs-rng.o
> diff --git a/drivers/char/hw_random/mpfs-rng.c b/drivers/char/hw_random/mpfs-rng.c
> new file mode 100644
> index 000000000000..a103c765d021
> --- /dev/null
> +++ b/drivers/char/hw_random/mpfs-rng.c
> @@ -0,0 +1,103 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * Microchip PolarFire SoC (MPFS) hardware random driver
> + *
> + * Copyright (c) 2020-2022 Microchip Corporation. All rights reserved.
> + *
> + * Author: Conor Dooley <conor.dooley@...rochip.com>
> + */
> +
> +#include <linux/module.h>
> +#include <linux/hw_random.h>
> +#include <linux/platform_device.h>
> +#include <soc/microchip/mpfs.h>
> +
> +#define CMD_OPCODE	0x21
> +#define CMD_DATA_SIZE	0U
> +#define CMD_DATA	NULL
> +#define MBOX_OFFSET	0U
> +#define RESP_OFFSET	0U
> +#define RNG_RESP_BYTES	32U
> +
> +struct mpfs_rng {
> +	struct mpfs_sys_controller *sys_controller;
> +	struct hwrng rng;
> +};
> +
> +static int mpfs_rng_read(struct hwrng *rng, void *buf, size_t max, bool wait)
> +{
> +	struct mpfs_rng *rng_priv = container_of(rng, struct mpfs_rng, rng);
> +	u32 response_msg[RNG_RESP_BYTES / sizeof(u32)];
> +	unsigned int count = 0, copy_size_bytes;
> +	int ret;
> +
> +	struct mpfs_mss_response response = {
> +		.resp_status = 0U,
> +		.resp_msg = (u32 *)response_msg,
> +		.resp_size = RNG_RESP_BYTES
> +	};
> +	struct mpfs_mss_msg msg = {
> +		.cmd_opcode = CMD_OPCODE,
> +		.cmd_data_size = CMD_DATA_SIZE,
> +		.response = &response,
> +		.cmd_data = CMD_DATA,
> +		.mbox_offset = MBOX_OFFSET,
> +		.resp_offset = RESP_OFFSET
> +	};
> +
> +	while (count < max) {
> +		ret = mpfs_blocking_transaction(rng_priv->sys_controller, &msg);
> +		if (ret)
> +			return ret;
> +
> +		copy_size_bytes = max - count > RNG_RESP_BYTES ? RNG_RESP_BYTES : max - count;
> +		memcpy(buf + count, response_msg, copy_size_bytes);
> +
> +		count += copy_size_bytes;
> +		if (!wait)
> +			break;
> +	}
> +
> +	return count;
> +}
> +
> +static int mpfs_rng_probe(struct platform_device *pdev)
> +{
> +	struct device *dev = &pdev->dev;
> +	struct mpfs_rng *rng_priv;
> +	int ret;
> +
> +	rng_priv = devm_kzalloc(dev, sizeof(*rng_priv), GFP_KERNEL);
> +	if (!rng_priv)
> +		return -ENOMEM;
> +
> +	rng_priv->sys_controller =  mpfs_sys_controller_get(&pdev->dev);
> +	if (IS_ERR(rng_priv->sys_controller))
> +		return dev_err_probe(dev, PTR_ERR(rng_priv->sys_controller),
> +				     "Failed to register system controller hwrng sub device\n");
> +
> +	rng_priv->rng.read = mpfs_rng_read;
> +	rng_priv->rng.name = pdev->name;

Is there also some quality estimation, or should this hwrng only be trusted
if it passes validation by userspace?

Thanks,
	Dominik