[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]
Message-ID: <5f79e76b-1333-159c-2dc7-0f7e8927e4df@collabora.com>
Date: Mon, 14 Mar 2022 11:18:25 +0100
From: AngeloGioacchino Del Regno
<angelogioacchino.delregno@...labora.com>
To: Jiaxin Yu <jiaxin.yu@...iatek.com>, broonie@...nel.org,
robh+dt@...nel.org
Cc: aaronyu@...gle.com, matthias.bgg@...il.com, trevor.wu@...iatek.com,
tzungbi@...gle.com, julianbraha@...il.com,
alsa-devel@...a-project.org, devicetree@...r.kernel.org,
linux-arm-kernel@...ts.infradead.org,
linux-mediatek@...ts.infradead.org, linux-kernel@...r.kernel.org,
Project_Global_Chrome_Upstream_Group@...iatek.com
Subject: Re: [v3 03/19] ASoC: mediatek: mt8186: support audsys clock control
Il 13/03/22 16:10, Jiaxin Yu ha scritto:
> Add mt8186 audio cg control. Audio clock gates are registered to
> CCF for reference count and clock parent management.
>
> Signed-off-by: Jiaxin Yu <jiaxin.yu@...iatek.com>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@...labora.com>
> ---
> sound/soc/mediatek/mt8186/mt8186-audsys-clk.c | 150 ++++++++++++++++++
> sound/soc/mediatek/mt8186/mt8186-audsys-clk.h | 15 ++
> .../soc/mediatek/mt8186/mt8186-audsys-clkid.h | 45 ++++++
> 3 files changed, 210 insertions(+)
> create mode 100644 sound/soc/mediatek/mt8186/mt8186-audsys-clk.c
> create mode 100644 sound/soc/mediatek/mt8186/mt8186-audsys-clk.h
> create mode 100644 sound/soc/mediatek/mt8186/mt8186-audsys-clkid.h
>
Powered by blists - more mailing lists