linux-kernel - Re: [PATCH 3/3] irqchip/gic-v3: Relax polling of GIC{R,D}

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Message-ID: <871qz1zyxu.wl-maz@kernel.org>
Date:   Wed, 16 Mar 2022 15:42:21 +0000
From:   Marc Zyngier <maz@...nel.org>
To:     Andre Przywara <andre.przywara@....com>
Cc:     linux-kernel@...r.kernel.org,
        Lorenzo Pieralisi <lorenzo.pieralisi@....com>,
        Thomas Gleixner <tglx@...utronix.de>,
        Eric Auger <eric.auger@...hat.com>
Subject: Re: [PATCH 3/3] irqchip/gic-v3: Relax polling of GIC{R,D}_CTLR.RWP

On Wed, 16 Mar 2022 14:54:03 +0000,
Andre Przywara <andre.przywara@....com> wrote:
> 
> On Tue, 15 Mar 2022 16:50:34 +0000
> Marc Zyngier <maz@...nel.org> wrote:
> 
> Hi,
> 
> > Recent work on the KVM GIC emulation has revealed that the GICv3
> > driver is a bit RWP-happy, as it polls this bit for each and
> > every write MMIO access involving a single interrupt.
> >
> > As it turns out, polling RWP is only required when:
> > - Disabling an SGI, PPI or SPI
> > - Disabling LPIs at the redistributor level
> > - Disabling groups
> > - Enabling ARE
> > - Dealing with DPG*
> >
> > Simplify the driver by removing all the other instances of RWP
> > polling, and add the one that was missing when enabling the distributor
> > (as that's where we set ARE).
> 
> Don't we need an explicit call to wait_for_rwp() now for:
> gic_irq_set_irqchip_state(IRQCHIP_STATE_MASKED, true) ?

Ah, yes, I missed that one. Thanks.

> IMPORTANT NOTICE: The contents of this email [...]

The ARM IT crap is firing again. Wrong SMTP server?

	M.

-- 
Without deviation from the norm, progress is not possible.