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Message-ID: <c3d39666-52ae-42ba-eaa2-7a0ca489f766@redhat.com>
Date: Thu, 17 Mar 2022 11:04:18 +0100
From: David Hildenbrand <david@...hat.com>
To: Catalin Marinas <catalin.marinas@....com>
Cc: linux-kernel@...r.kernel.org,
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Subject: Re: [PATCH v1 4/7] arm64/pgtable: support
__HAVE_ARCH_PTE_SWP_EXCLUSIVE
On 16.03.22 19:27, Catalin Marinas wrote:
> On Tue, Mar 15, 2022 at 03:18:34PM +0100, David Hildenbrand wrote:
>> diff --git a/arch/arm64/include/asm/pgtable-prot.h b/arch/arm64/include/asm/pgtable-prot.h
>> index b1e1b74d993c..62e0ebeed720 100644
>> --- a/arch/arm64/include/asm/pgtable-prot.h
>> +++ b/arch/arm64/include/asm/pgtable-prot.h
>> @@ -14,6 +14,7 @@
>> * Software defined PTE bits definition.
>> */
>> #define PTE_WRITE (PTE_DBM) /* same as DBM (51) */
>> +#define PTE_SWP_EXCLUSIVE (_AT(pteval_t, 1) << 2) /* only for swp ptes */
>
> I think we can use bit 1 here.
>
>> @@ -909,12 +925,13 @@ static inline pmd_t pmdp_establish(struct vm_area_struct *vma,
>> /*
>> * Encode and decode a swap entry:
>> * bits 0-1: present (must be zero)
>> - * bits 2-7: swap type
>> + * bits 2: remember PG_anon_exclusive
>> + * bits 3-7: swap type
>> * bits 8-57: swap offset
>> * bit 58: PTE_PROT_NONE (must be zero)
>
> I don't remember exactly why we reserved bits 0 and 1 when, from the
> hardware perspective, it's sufficient for bit 0 to be 0 and the whole
> pte becomes invalid. We use bit 1 as the 'table' bit (when 0 at pmd
> level, it's a huge page) but we shouldn't check for this on a swap
> entry.
You mean
arch/arm64/include/asm/pgtable-hwdef.h:#define PTE_TABLE_BIT (_AT(pteval_t, 1) << 1)
right?
I wonder why it even exists, for arm64 I only spot:
arch/arm64/include/asm/pgtable.h:#define pte_mkhuge(pte) (__pte(pte_val(pte) & ~PTE_TABLE_BIT))
I don't really see code that sets PTE_TABLE_BIT.
Similarly, I don't see code that sets PMD_TABLE_BIT/PUD_TABLE_BIT/P4D_TABLE_BIT.
Most probably setting code is not using the defines, that's why I'm not finding it.
--
Thanks,
David / dhildenb
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