[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]
Message-ID: <YjMbHKwtOKJTfVIh@hirez.programming.kicks-ass.net>
Date: Thu, 17 Mar 2022 12:27:24 +0100
From: Peter Zijlstra <peterz@...radead.org>
To: Sandipan Das <sandipan.das@....com>
Cc: linux-kernel@...r.kernel.org, linux-perf-users@...r.kernel.org,
x86@...nel.org, bp@...en8.de, dave.hansen@...ux.intel.com,
acme@...nel.org, mark.rutland@....com,
alexander.shishkin@...ux.intel.com, namhyung@...nel.org,
jolsa@...nel.org, tglx@...utronix.de, mingo@...hat.com,
pbonzini@...hat.com, jmattson@...gle.com, like.xu.linux@...il.com,
eranian@...gle.com, ananth.narayan@....com, ravi.bangoria@....com,
santosh.shukla@....com
Subject: Re: [PATCH 3/7] perf/x86/amd/core: Detect PerfMonV2 support
On Thu, Mar 17, 2022 at 11:58:32AM +0530, Sandipan Das wrote:
> AMD Performance Monitoring Version 2 (PerfMonV2) introduces
> some new Core PMU features such as detection of the number
> of available PMCs and managing PMCs using global registers
> namely, PerfCntrGlobalCtl and PerfCntrGlobalStatus.
>
> Clearing PerfCntrGlobalCtl and PerfCntrGlobalStatus ensures
> that all PMCs are inactive and have no pending overflows
> when CPUs are onlined or offlined.
>
> The PMU version (x86_pmu.version) now indicates PerfMonV2
> support and will be used to bypass the new features on
> unsupported processors.
>
> Signed-off-by: Sandipan Das <sandipan.das@....com>
> ---
> +static void amd_pmu_cpu_reset(int cpu)
> +{
> + if (x86_pmu.version < 2)
> + return;
> +
> + /* Clear enable bits i.e. PerfCntrGlobalCtl.PerfCntrEn */
> + wrmsrl_on_cpu(cpu, MSR_AMD64_PERF_CNTR_GLOBAL_CTL, 0);
> +
> + /* Clear overflow bits i.e. PerfCntrGLobalStatus.PerfCntrOvfl */
> + wrmsrl_on_cpu(cpu, MSR_AMD64_PERF_CNTR_GLOBAL_STATUS_CLR,
> + amd_pmu_global_cntr_mask);
> +}
I think these can be wrmsrl() both starting and dead run on the target
cpu.
Powered by blists - more mailing lists