linux-kernel - Re: [PATCH v2 1/8] dt-bindings: pinctrl: mvebu: Document bindings for AC5

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Message-ID: <YjNCSENOP8EyWArw@lunn.ch>
Date:   Thu, 17 Mar 2022 15:14:32 +0100
From:   Andrew Lunn <andrew@...n.ch>
To:     Krzysztof Kozlowski <krzysztof.kozlowski@...onical.com>
Cc:     Chris Packham <Chris.Packham@...iedtelesis.co.nz>,
        "robh+dt@...nel.org" <robh+dt@...nel.org>,
        "linus.walleij@...aro.org" <linus.walleij@...aro.org>,
        "catalin.marinas@....com" <catalin.marinas@....com>,
        "gregory.clement@...tlin.com" <gregory.clement@...tlin.com>,
        "sebastian.hesselbarth@...il.com" <sebastian.hesselbarth@...il.com>,
        "devicetree@...r.kernel.org" <devicetree@...r.kernel.org>,
        "linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
        "linux-gpio@...r.kernel.org" <linux-gpio@...r.kernel.org>,
        "linux-arm-kernel@...ts.infradead.org" 
        <linux-arm-kernel@...ts.infradead.org>
Subject: Re: [PATCH v2 1/8] dt-bindings: pinctrl: mvebu: Document bindings
 for AC5

> What do you mean "driver fails to load"? You control the driver, don't
> you?

It is a thin wrapper around the mvebu driver, which does all the real
work. So no, Chris does not really control what the core of the driver
does.

The existing binding documentation says:

    * Marvell Armada 37xx SoC pin and gpio controller

    Each Armada 37xx SoC come with two pin and gpio controller one for
    the south bridge and the other for the north bridge.

    Inside this set of register the gpio latch allows exposing some
    configuration of the SoC and especially the clock frequency of the
    xtal. Hence, this node is a represent as syscon allowing sharing
    the register between multiple hardware block.


So the syscon is there to allow the clock driver to share the register
space.

	Andrew