linux-kernel - Re: [PATCH 4/5 v2] dt-bindings: gnss: Add two more chips

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives

Hash Suite: Windows password security audit tool. GUI, reports in PDF.

[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]

Message-ID: <d1fab3e6-a9ee-0d3e-9d4b-d082317d8b72@kernel.org>
Date:   Fri, 18 Mar 2022 10:29:32 +0100
From:   Krzysztof Kozlowski <krzk@...nel.org>
To:     Linus Walleij <linus.walleij@...aro.org>,
        Johan Hovold <johan@...nel.org>
Cc:     linux-kernel@...r.kernel.org, devicetree@...r.kernel.org
Subject: Re: [PATCH 4/5 v2] dt-bindings: gnss: Add two more chips

On 17/03/2022 23:58, Linus Walleij wrote:
> The CSR GSD4t is a CSR product using the SiRFstarIV core, and
> the CSR CSRG05TA03-ICJE-R is a CSR product using the SiRFstarV
> core.
> 
> These chips have a SRESETN line that can be pulled low to hard
> reset the chip and in some designs this is connected to a GPIO,
> so add this as an optional property.
> 
> Update the example with a reset line so users see that it need
> to be tagged as active low.
> 
> Cc: devicetree@...r.kernel.org
> Cc: Krzysztof Kozlowski <krzk@...nel.org>
> Signed-off-by: Linus Walleij <linus.walleij@...aro.org>
> ---
> ChangeLog v1->v2:
> - Add maxItems: 1 to the reset-gpios
> ---
>  Documentation/devicetree/bindings/gnss/sirfstar.yaml | 8 ++++++++
>  1 file changed, 8 insertions(+)
> 


Reviewed-by: Krzysztof Kozlowski <krzk@...nel.org>


Best regards,
Krzysztof