linux-kernel - Re: [PATCH v2 1/2] dt-bindings: phy: mediatek: Add YAML schema for PCIe PHY

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives

Hash Suite: Windows password security audit tool. GUI, reports in PDF.

[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]

Message-ID: <e0adbb4d-aa87-49ea-d79f-11c5f4fc4bdd@collabora.com>
Date:   Fri, 18 Mar 2022 14:56:23 +0100
From:   AngeloGioacchino Del Regno 
        <angelogioacchino.delregno@...labora.com>
To:     Krzysztof Kozlowski <krzk@...nel.org>,
        Jianjun Wang <jianjun.wang@...iatek.com>,
        Chunfeng Yun <chunfeng.yun@...iatek.com>,
        Kishon Vijay Abraham I <kishon@...com>,
        Vinod Koul <vkoul@...nel.org>,
        Rob Herring <robh+dt@...nel.org>,
        Matthias Brugger <matthias.bgg@...il.com>,
        Chen-Yu Tsai <wenst@...omium.org>
Cc:     linux-arm-kernel@...ts.infradead.org,
        linux-mediatek@...ts.infradead.org, linux-phy@...ts.infradead.org,
        devicetree@...r.kernel.org, linux-kernel@...r.kernel.org,
        rex-bc.chen@...iatek.com, randy.wu@...iatek.com,
        jieyy.yang@...iatek.com, chuanjia.liu@...iatek.com,
        qizhong.cheng@...iatek.com, jian.yang@...iatek.com
Subject: Re: [PATCH v2 1/2] dt-bindings: phy: mediatek: Add YAML schema for
 PCIe PHY

Il 18/03/22 14:51, Krzysztof Kozlowski ha scritto:
> On 18/03/2022 12:12, AngeloGioacchino Del Regno wrote:
>> Il 18/03/22 10:54, Jianjun Wang ha scritto:
>>> Add YAML schema documentation for PCIe PHY on MediaTek chipsets.
>>>
>>> Signed-off-by: Jianjun Wang <jianjun.wang@...iatek.com>
>>> ---
>>>    .../bindings/phy/mediatek,pcie-phy.yaml       | 75 +++++++++++++++++++
>>>    1 file changed, 75 insertions(+)
>>>    create mode 100644 Documentation/devicetree/bindings/phy/mediatek,pcie-phy.yaml
>>>
>>> diff --git a/Documentation/devicetree/bindings/phy/mediatek,pcie-phy.yaml b/Documentation/devicetree/bindings/phy/mediatek,pcie-phy.yaml
>>> new file mode 100644
>>> index 000000000000..868bf976568b
>>> --- /dev/null
>>> +++ b/Documentation/devicetree/bindings/phy/mediatek,pcie-phy.yaml
>>> @@ -0,0 +1,75 @@
>>> +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
>>> +%YAML 1.2
>>> +---
>>> +$id: http://devicetree.org/schemas/phy/mediatek,pcie-phy.yaml#
>>> +$schema: http://devicetree.org/meta-schemas/core.yaml#
>>> +
>>> +title: MediaTek PCIe PHY
>>> +
>>> +maintainers:
>>> +  - Jianjun Wang <jianjun.wang@...iatek.com>
>>> +
>>> +description: |
>>> +  The PCIe PHY supports physical layer functionality for PCIe Gen3 port.
>>> +
>>> +properties:
>>> +  compatible:
>>> +    const: mediatek,mt8195-pcie-phy
>>
>> Since I don't expect this driver to be only for MT8195, but to be extended to
>> support some more future MediaTek SoCs and, depending on the number of differences
>> in the possible future Gen4 PHYs, even different gen's, I propose to add a generic
>> compatible as const.
>>
>> So you'll have something like:
>>
>> - enum:
>>       - mediatek,mt8195-pcie-phy
>> - const: mediatek,pcie-gen3-phy
> 
> I am not sure if this is a good idea. How sure are you that there will
> be no different PCIe Gen3 PHY not compatible with this one?
> 
> 

Thanks for pointing that out, I have underestimated this option.

Perhaps Jianjun may be more informed about whether my proposal is valid or not.

Cheers,
Angelo

> Best regards,
> Krzysztof