linux-kernel - Re: [PATCH v8 0/7] CTU CAN FD open-source IP core SocketCAN driver, PCI, platform integration and documentation

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives

Hash Suite: Windows password security audit tool. GUI, reports in PDF.

[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]

Date:   Tue, 22 Mar 2022 10:22:12 +0100
From:   Marc Kleine-Budde <mkl@...gutronix.de>
To:     Pavel Pisa <pisa@....felk.cvut.cz>
Cc:     linux-can@...r.kernel.org, devicetree@...r.kernel.org,
        Oliver Hartkopp <socketcan@...tkopp.net>,
        Wolfgang Grandegger <wg@...ndegger.com>,
        David Miller <davem@...emloft.net>,
        Rob Herring <robh+dt@...nel.org>, mark.rutland@....com,
        Carsten Emde <c.emde@...dl.org>, armbru@...hat.com,
        netdev@...r.kernel.org, linux-kernel@...r.kernel.org,
        Marin Jerabek <martin.jerabek01@...il.com>,
        Ondrej Ille <ondrej.ille@...il.com>,
        Jiri Novak <jnovak@....cvut.cz>,
        Jaroslav Beran <jara.beran@...il.com>,
        Petr Porazil <porazil@...ron.com>, Pavel Machek <pavel@....cz>,
        Drew Fustini <pdp7pdp7@...il.com>
Subject: Re: [PATCH v8 0/7] CTU CAN FD open-source IP core SocketCAN driver,
 PCI, platform integration and documentation

On 22.03.2022 09:18:32, Pavel Pisa wrote:
> > The driver looks much better now. Good work. Please have a look at the
> > TX path of the mcp251xfd driver, especially the tx_stop_queue and
> > tx_wake_queue in mcp251xfd_start_xmit() and mcp251xfd_handle_tefif(). A
> > lockless implementation should work in your hardware, too.
> 
> Is this blocker for now? I would like to start with years tested base.

Makes sense.

> We have HW timestamping implemented for actual stable CTU CAN FD IP core 
> version, support for variable number of TX buffers which count can be 
> parameterized up to 8 in the prepared version and long term desire to 
> configurable-SW defined multi-queue which our HW interface allows to 
> dynamically server by á TX buffers. But plan is to keep combinations
> of the design and driver compatible from the actual revision.

Is the number of RX and TX buffers and TX queues auto detectable by
software, or do we need DT bindings for this?

> I would be happy if we can agree on some base/minimal support and get
> it into mainline and use it as base for the followup patch series.
> 
> I understand that I have sent code late for actual merge window,
> but I am really loaded by teaching, related RISC-V simulator
> https://github.com/cvut/qtrvsim , ESA and robotic projects
> at company. So I would prefer to go step by step and cooperate
> on updates and testing with my diploma students.

The net-next merge window closed with Monday evening, so this driver
will go into net-next for v5.19.

> > BTW: The PROP_SEG/PHASE_SEG1 issue is known:
> > > +A curious reader will notice that the durations of the segments PROP_SEG
> > > +and PHASE_SEG1 are not determined separately but rather combined and
> > > +then, by default, the resulting TSEG1 is evenly divided between PROP_SEG
> > > +and PHASE_SEG1.
> >
> > and the flexcan IP core in CAN-FD mode has the same problem. When
> > working on the bit timing parameter, I'll plan to have separate
> > PROP_SEG/PHASE_SEG1 min/max in the kernel, so that the bit timing
> > algorithm can take care of this.
> 
> Hmm, when I have thought about that years ago I have not noticed real
> difference when time quanta is move between PROP_SEG and PHASE_SEG1.
> So for me it had no influence on the algorithm computation and
> could be done on the chip level when minimal and maximal sum is
> respected. But may it be I have overlooked something and there is
> difference for CAN FD.  May it be my colleagues Jiri Novak and 
> Ondrej Ille are more knowable.

Jiri, Ondrej, I'm interested in details :)

> As for the optimal timequantas per bit value, I agree that it
> is not so simple. In the fact SJW and even tipple-sampling
> should be defined in percentage of bit time

I thought of specifying SJW in a relative value, too.

> and then all should be optimized together

SJW has no influence on the bit rate and sample point. Although SJW is
max phase seg 2, so it's maximum is influenced by the sample point.

> and even combination with slight bitrate error should be preferred
> against other exact matching when there is significant difference in
> the other parameters values.

Since linux-4.8, i.e.

| 7da29f97d6c8 can: dev: can-calc-bit-timing(): better sample point calculation

the algorithm optimizes for best bit minimal absolute bit rate error
first and then for minimal sample point error. The sample point must be
<= the nominal sample point. I have some experiments where the algorithm
optimizes the absolute sample point error.

For more complicated bit timing optimization you need to combine the
bitrate error and the sample point error into a function that needs to
be minimized.

> But I am not ready to dive into it till our ESA space NanoXplore
> FPGA project passes final stage... 

Ok

> By the way we have received report from Andrew Dennison about
> successful integration of CTU CAN FD into Litex based RISC-V
> system. Tested with the Linux our Linux kernel driver.

That sounds interesting!

> The first iteration there, but he reported that some corrections
> from his actual development needs to be added to the public
> repo still to be usable out of the box
> 
>   https://github.com/AndrewD/litecan

Nice!

regards,
Marc

-- 
Pengutronix e.K.                 | Marc Kleine-Budde           |
Embedded Linux                   | https://www.pengutronix.de  |
Vertretung West/Dortmund         | Phone: +49-231-2826-924     |
Amtsgericht Hildesheim, HRA 2686 | Fax:   +49-5121-206917-5555 |

Download attachment "signature.asc" of type "application/pgp-signature" (489 bytes)