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Message-ID: <2ef7d715-8b1f-8264-819d-6eb55beb773c@gmail.com>
Date: Fri, 25 Mar 2022 11:58:58 +0100
From: Matthias Brugger <matthias.bgg@...il.com>
To: Allen-KH Cheng <allen-kh.cheng@...iatek.com>,
Rob Herring <robh+dt@...nel.org>,
Krzysztof Kozlowski <krzysztof.kozlowski@...onical.com>
Cc: Project_Global_Chrome_Upstream_Group@...iatek.com,
devicetree@...r.kernel.org, linux-arm-kernel@...ts.infradead.org,
linux-kernel@...r.kernel.org, linux-mediatek@...ts.infradead.org,
Chen-Yu Tsai <wenst@...omium.org>,
Ryder Lee <ryder.lee@...nel.org>,
Hui Liu <hui.liu@...iatek.com>
Subject: Re: [PATCH v4 14/22] arm64: dts: mt8192: Add m4u and smi nodes
On 18/03/2022 15:45, Allen-KH Cheng wrote:
> Add m4u and smi nodes for mt8192 SoC
>
> Signed-off-by: Allen-KH Cheng <allen-kh.cheng@...iatek.com>
> Reviewed-by: Nícolas F. R. A. Prado <nfraprado@...labora.com>
> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@...labora.com>
Applied thanks
> ---
> arch/arm64/boot/dts/mediatek/mt8192.dtsi | 190 +++++++++++++++++++++++
> 1 file changed, 190 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> index 6b769fa5b427..4addf6ddd86d 100644
> --- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> +++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> @@ -9,6 +9,7 @@
> #include <dt-bindings/gce/mt8192-gce.h>
> #include <dt-bindings/interrupt-controller/arm-gic.h>
> #include <dt-bindings/interrupt-controller/irq.h>
> +#include <dt-bindings/memory/mt8192-larb-port.h>
> #include <dt-bindings/pinctrl/mt8192-pinfunc.h>
> #include <dt-bindings/phy/phy.h>
> #include <dt-bindings/power/mt8192-power.h>
> @@ -1204,24 +1205,114 @@
> #clock-cells = <1>;
> };
>
> + smi_common: smi@...02000 {
> + compatible = "mediatek,mt8192-smi-common";
> + reg = <0 0x14002000 0 0x1000>;
> + clocks = <&mmsys CLK_MM_SMI_COMMON>,
> + <&mmsys CLK_MM_SMI_INFRA>,
> + <&mmsys CLK_MM_SMI_GALS>,
> + <&mmsys CLK_MM_SMI_GALS>;
> + clock-names = "apb", "smi", "gals0", "gals1";
> + power-domains = <&spm MT8192_POWER_DOMAIN_DISP>;
> + };
> +
> + larb0: larb@...03000 {
> + compatible = "mediatek,mt8192-smi-larb";
> + reg = <0 0x14003000 0 0x1000>;
> + mediatek,larb-id = <0>;
> + mediatek,smi = <&smi_common>;
> + clocks = <&clk26m>, <&clk26m>;
> + clock-names = "apb", "smi";
> + power-domains = <&spm MT8192_POWER_DOMAIN_DISP>;
> + };
> +
> + larb1: larb@...04000 {
> + compatible = "mediatek,mt8192-smi-larb";
> + reg = <0 0x14004000 0 0x1000>;
> + mediatek,larb-id = <1>;
> + mediatek,smi = <&smi_common>;
> + clocks = <&clk26m>, <&clk26m>;
> + clock-names = "apb", "smi";
> + power-domains = <&spm MT8192_POWER_DOMAIN_DISP>;
> + };
> +
> + iommu0: m4u@...1d000 {
> + compatible = "mediatek,mt8192-m4u";
> + reg = <0 0x1401d000 0 0x1000>;
> + mediatek,larbs = <&larb0>, <&larb1>, <&larb2>,
> + <&larb4>, <&larb5>, <&larb7>,
> + <&larb9>, <&larb11>, <&larb13>,
> + <&larb14>, <&larb16>, <&larb17>,
> + <&larb18>, <&larb19>, <&larb20>;
> + interrupts = <GIC_SPI 277 IRQ_TYPE_LEVEL_HIGH 0>;
> + clocks = <&mmsys CLK_MM_SMI_IOMMU>;
> + clock-names = "bclk";
> + power-domains = <&spm MT8192_POWER_DOMAIN_DISP>;
> + #iommu-cells = <1>;
> + };
> +
> imgsys: clock-controller@...20000 {
> compatible = "mediatek,mt8192-imgsys";
> reg = <0 0x15020000 0 0x1000>;
> #clock-cells = <1>;
> };
>
> + larb9: larb@...2e000 {
> + compatible = "mediatek,mt8192-smi-larb";
> + reg = <0 0x1502e000 0 0x1000>;
> + mediatek,larb-id = <9>;
> + mediatek,smi = <&smi_common>;
> + clocks = <&imgsys CLK_IMG_LARB9>,
> + <&imgsys CLK_IMG_LARB9>;
> + clock-names = "apb", "smi";
> + power-domains = <&spm MT8192_POWER_DOMAIN_ISP>;
> + };
> +
> imgsys2: clock-controller@...20000 {
> compatible = "mediatek,mt8192-imgsys2";
> reg = <0 0x15820000 0 0x1000>;
> #clock-cells = <1>;
> };
>
> + larb11: larb@...2e000 {
> + compatible = "mediatek,mt8192-smi-larb";
> + reg = <0 0x1582e000 0 0x1000>;
> + mediatek,larb-id = <11>;
> + mediatek,smi = <&smi_common>;
> + clocks = <&imgsys2 CLK_IMG2_LARB11>,
> + <&imgsys2 CLK_IMG2_LARB11>;
> + clock-names = "apb", "smi";
> + power-domains = <&spm MT8192_POWER_DOMAIN_ISP2>;
> + };
> +
> + larb5: larb@...0d000 {
> + compatible = "mediatek,mt8192-smi-larb";
> + reg = <0 0x1600d000 0 0x1000>;
> + mediatek,larb-id = <5>;
> + mediatek,smi = <&smi_common>;
> + clocks = <&vdecsys_soc CLK_VDEC_SOC_LARB1>,
> + <&vdecsys_soc CLK_VDEC_SOC_LARB1>;
> + clock-names = "apb", "smi";
> + power-domains = <&spm MT8192_POWER_DOMAIN_VDEC>;
> + };
> +
> vdecsys_soc: clock-controller@...0f000 {
> compatible = "mediatek,mt8192-vdecsys_soc";
> reg = <0 0x1600f000 0 0x1000>;
> #clock-cells = <1>;
> };
>
> + larb4: larb@...2e000 {
> + compatible = "mediatek,mt8192-smi-larb";
> + reg = <0 0x1602e000 0 0x1000>;
> + mediatek,larb-id = <4>;
> + mediatek,smi = <&smi_common>;
> + clocks = <&vdecsys CLK_VDEC_SOC_LARB1>,
> + <&vdecsys CLK_VDEC_SOC_LARB1>;
> + clock-names = "apb", "smi";
> + power-domains = <&spm MT8192_POWER_DOMAIN_VDEC2>;
> + };
> +
> vdecsys: clock-controller@...2f000 {
> compatible = "mediatek,mt8192-vdecsys";
> reg = <0 0x1602f000 0 0x1000>;
> @@ -1234,12 +1325,78 @@
> #clock-cells = <1>;
> };
>
> + larb7: larb@...10000 {
> + compatible = "mediatek,mt8192-smi-larb";
> + reg = <0 0x17010000 0 0x1000>;
> + mediatek,larb-id = <7>;
> + mediatek,smi = <&smi_common>;
> + clocks = <&vencsys CLK_VENC_SET0_LARB>,
> + <&vencsys CLK_VENC_SET1_VENC>;
> + clock-names = "apb", "smi";
> + power-domains = <&spm MT8192_POWER_DOMAIN_VENC>;
> + };
> +
> camsys: clock-controller@...00000 {
> compatible = "mediatek,mt8192-camsys";
> reg = <0 0x1a000000 0 0x1000>;
> #clock-cells = <1>;
> };
>
> + larb13: larb@...01000 {
> + compatible = "mediatek,mt8192-smi-larb";
> + reg = <0 0x1a001000 0 0x1000>;
> + mediatek,larb-id = <13>;
> + mediatek,smi = <&smi_common>;
> + clocks = <&camsys CLK_CAM_CAM>,
> + <&camsys CLK_CAM_LARB13>;
> + clock-names = "apb", "smi";
> + power-domains = <&spm MT8192_POWER_DOMAIN_CAM>;
> + };
> +
> + larb14: larb@...02000 {
> + compatible = "mediatek,mt8192-smi-larb";
> + reg = <0 0x1a002000 0 0x1000>;
> + mediatek,larb-id = <14>;
> + mediatek,smi = <&smi_common>;
> + clocks = <&camsys CLK_CAM_CAM>,
> + <&camsys CLK_CAM_LARB14>;
> + clock-names = "apb", "smi";
> + power-domains = <&spm MT8192_POWER_DOMAIN_CAM>;
> + };
> +
> + larb16: larb@...0f000 {
> + compatible = "mediatek,mt8192-smi-larb";
> + reg = <0 0x1a00f000 0 0x1000>;
> + mediatek,larb-id = <16>;
> + mediatek,smi = <&smi_common>;
> + clocks = <&camsys_rawa CLK_CAM_RAWA_CAM>,
> + <&camsys_rawa CLK_CAM_RAWA_LARBX>;
> + clock-names = "apb", "smi";
> + power-domains = <&spm MT8192_POWER_DOMAIN_CAM_RAWA>;
> + };
> +
> + larb17: larb@...10000 {
> + compatible = "mediatek,mt8192-smi-larb";
> + reg = <0 0x1a010000 0 0x1000>;
> + mediatek,larb-id = <17>;
> + mediatek,smi = <&smi_common>;
> + clocks = <&camsys_rawb CLK_CAM_RAWB_CAM>,
> + <&camsys_rawb CLK_CAM_RAWB_LARBX>;
> + clock-names = "apb", "smi";
> + power-domains = <&spm MT8192_POWER_DOMAIN_CAM_RAWB>;
> + };
> +
> + larb18: larb@...11000 {
> + compatible = "mediatek,mt8192-smi-larb";
> + reg = <0 0x1a011000 0 0x1000>;
> + mediatek,larb-id = <18>;
> + mediatek,smi = <&smi_common>;
> + clocks = <&camsys_rawc CLK_CAM_RAWC_LARBX>,
> + <&camsys_rawc CLK_CAM_RAWC_CAM>;
> + clock-names = "apb", "smi";
> + power-domains = <&spm MT8192_POWER_DOMAIN_CAM_RAWC>;
> + };
> +
> camsys_rawa: clock-controller@...4f000 {
> compatible = "mediatek,mt8192-camsys_rawa";
> reg = <0 0x1a04f000 0 0x1000>;
> @@ -1264,10 +1421,43 @@
> #clock-cells = <1>;
> };
>
> + larb20: larb@...0f000 {
> + compatible = "mediatek,mt8192-smi-larb";
> + reg = <0 0x1b00f000 0 0x1000>;
> + mediatek,larb-id = <20>;
> + mediatek,smi = <&smi_common>;
> + clocks = <&ipesys CLK_IPE_SMI_SUBCOM>,
> + <&ipesys CLK_IPE_LARB20>;
> + clock-names = "apb", "smi";
> + power-domains = <&spm MT8192_POWER_DOMAIN_IPE>;
> + };
> +
> + larb19: larb@...0f000 {
> + compatible = "mediatek,mt8192-smi-larb";
> + reg = <0 0x1b10f000 0 0x1000>;
> + mediatek,larb-id = <19>;
> + mediatek,smi = <&smi_common>;
> + clocks = <&ipesys CLK_IPE_SMI_SUBCOM>,
> + <&ipesys CLK_IPE_LARB19>;
> + clock-names = "apb", "smi";
> + power-domains = <&spm MT8192_POWER_DOMAIN_IPE>;
> + };
> +
> mdpsys: clock-controller@...00000 {
> compatible = "mediatek,mt8192-mdpsys";
> reg = <0 0x1f000000 0 0x1000>;
> #clock-cells = <1>;
> };
> +
> + larb2: larb@...02000 {
> + compatible = "mediatek,mt8192-smi-larb";
> + reg = <0 0x1f002000 0 0x1000>;
> + mediatek,larb-id = <2>;
> + mediatek,smi = <&smi_common>;
> + clocks = <&mdpsys CLK_MDP_SMI0>,
> + <&mdpsys CLK_MDP_SMI0>;
> + clock-names = "apb", "smi";
> + power-domains = <&spm MT8192_POWER_DOMAIN_MDP>;
> + };
> };
> };
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