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Message-ID: <HK0PR06MB23073BAA6569EE0AD5527D00E61A9@HK0PR06MB2307.apcprd06.prod.outlook.com>
Date:   Fri, 25 Mar 2022 01:57:23 +0000
From:   Howard Chiu <howard_chiu@...eedtech.com>
To:     Jae Hyun Yoo <quic_jaehyoo@...cinc.com>,
        "robh+dt@...nel.org" <robh+dt@...nel.org>,
        Joel Stanley <joel@....id.au>,
        "andrew@...id.au" <andrew@...id.au>,
        "devicetree@...r.kernel.org" <devicetree@...r.kernel.org>,
        "linux-arm-kernel@...ts.infradead.org" 
        <linux-arm-kernel@...ts.infradead.org>,
        "linux-aspeed@...ts.ozlabs.org" <linux-aspeed@...ts.ozlabs.org>,
        "linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>
Subject: RE: [PATCH v1 2/3] dt-bindings: clock: Add AST2600 video engine reset
 definition

Hi Jae

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> -----Original Message-----
> From: Jae Hyun Yoo <quic_jaehyoo@...cinc.com>
> Sent: Thursday, March 24, 2022 9:51 PM
> To: Howard Chiu <howard_chiu@...eedtech.com>; robh+dt@...nel.org; Joel
> Stanley <joel@....id.au>; andrew@...id.au; devicetree@...r.kernel.org;
> linux-arm-kernel@...ts.infradead.org; linux-aspeed@...ts.ozlabs.org;
> linux-kernel@...r.kernel.org
> Subject: Re: [PATCH v1 2/3] dt-bindings: clock: Add AST2600 video engine reset
> definition
> 
> 
> 
> On 3/24/2022 12:27 AM, Howard Chiu wrote:
> > Reset bit for VE is 6
> >
> > Signed-off-by: Howard Chiu <howard_chiu@...eedtech.com>
> > ---
> >   include/dt-bindings/clock/ast2600-clock.h | 1 +
> >   1 file changed, 1 insertion(+)
> >
> > diff --git a/include/dt-bindings/clock/ast2600-clock.h
> > b/include/dt-bindings/clock/ast2600-clock.h
> > index 62b9520a00fd..a7d0ad9539eb 100644
> > --- a/include/dt-bindings/clock/ast2600-clock.h
> > +++ b/include/dt-bindings/clock/ast2600-clock.h
> > @@ -110,6 +110,7 @@
> >   #define ASPEED_RESET_PCIE_DEV_OEN	20
> >   #define ASPEED_RESET_PCIE_RC_O		19
> >   #define ASPEED_RESET_PCIE_RC_OEN	18
> > +#define ASPEED_RESET_VIDEO		6
> 
> You don't need to add 'resets' for video node in DT so it wouldn't be needed.
> 
Got it.
> -Jae
> 
> >   #define ASPEED_RESET_PCI_DP		5
> >   #define ASPEED_RESET_AHB		1
> >   #define ASPEED_RESET_SDRAM		0

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