linux-kernel - Re: [PATCH] perf/x86/intel: Don't extend the pseudo-encoding to GP counters

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Message-ID: <CABPqkBQS_VW4isEXBXzukWyUGqZSnR1G8c0p+MvK-MCVTjV2Ww@mail.gmail.com>
Date:   Mon, 28 Mar 2022 10:11:52 -0700
From:   Stephane Eranian <eranian@...gle.com>
To:     kan.liang@...ux.intel.com
Cc:     peterz@...radead.org, mingo@...hat.com,
        linux-kernel@...r.kernel.org, stable@...r.kernel.org
Subject: Re: [PATCH] perf/x86/intel: Don't extend the pseudo-encoding to GP counters

On Mon, Mar 28, 2022 at 8:50 AM <kan.liang@...ux.intel.com> wrote:
>
> From: Kan Liang <kan.liang@...ux.intel.com>
>
> The INST_RETIRED.PREC_DIST event (0x0100) doesn't count on SPR.
> perf stat -e cpu/event=0xc0,umask=0x0/,cpu/event=0x0,umask=0x1/ -C0
>
>  Performance counter stats for 'CPU(s) 0':
>
>            607,246      cpu/event=0xc0,umask=0x0/
>                  0      cpu/event=0x0,umask=0x1/
>
> The encoding for INST_RETIRED.PREC_DIST is pseudo-encoding, which
> doesn't work on the generic counters. However, current perf extends its
> mask to the generic counters.
>
> The pseudo event-code for a fixed counter must be 0x00. Check and avoid
> extending the mask for the fixed counter event which using the
> pseudo-encoding, e.g., ref-cycles and PREC_DIST event.
>
> With the patch,
> perf stat -e cpu/event=0xc0,umask=0x0/,cpu/event=0x0,umask=0x1/ -C0
>
>  Performance counter stats for 'CPU(s) 0':
>
>            583,184      cpu/event=0xc0,umask=0x0/
>            583,048      cpu/event=0x0,umask=0x1/
>
> Fixes: 2de71ee153ef ("perf/x86/intel: Fix ICL/SPR INST_RETIRED.PREC_DIST encodings")
> Signed-off-by: Kan Liang <kan.liang@...ux.intel.com>
> Cc: stable@...r.kernel.org
> ---
>  arch/x86/events/intel/core.c      | 6 +++++-
>  arch/x86/include/asm/perf_event.h | 5 +++++
>  2 files changed, 10 insertions(+), 1 deletion(-)
>
> diff --git a/arch/x86/events/intel/core.c b/arch/x86/events/intel/core.c
> index db32ef6..1d2e49d 100644
> --- a/arch/x86/events/intel/core.c
> +++ b/arch/x86/events/intel/core.c
> @@ -5668,7 +5668,11 @@ static void intel_pmu_check_event_constraints(struct event_constraint *event_con
>                         /* Disabled fixed counters which are not in CPUID */
>                         c->idxmsk64 &= intel_ctrl;
>
> -                       if (c->idxmsk64 != INTEL_PMC_MSK_FIXED_REF_CYCLES)
> +                       /*
> +                        * Don't extend the pseudo-encoding to the
> +                        * generic counters
> +                        */
> +                       if (!use_fixed_pseudo_encoding(c->code))
>                                 c->idxmsk64 |= (1ULL << num_counters) - 1;
>                 }
>                 c->idxmsk64 &=
> diff --git a/arch/x86/include/asm/perf_event.h b/arch/x86/include/asm/perf_event.h
> index 48e6ef56..cd85f03 100644
> --- a/arch/x86/include/asm/perf_event.h
> +++ b/arch/x86/include/asm/perf_event.h
> @@ -242,6 +242,11 @@ struct x86_pmu_capability {
>  #define INTEL_PMC_IDX_FIXED_SLOTS      (INTEL_PMC_IDX_FIXED + 3)
>  #define INTEL_PMC_MSK_FIXED_SLOTS      (1ULL << INTEL_PMC_IDX_FIXED_SLOTS)
>
> +static inline bool use_fixed_pseudo_encoding(u64 code)
> +{
> +       return !(code & 0xff);
> +}
> +
I ack the problem.

That does not take into account the old encoding for PREC_DIST 0x01c0
which is also forced to
fixed counter0 on ICL and should not be extended.

That also limits the options for the SLOTS events which can be
measured by a GP. Yet to work
with PERF_METRICS, it has to be programmed into fixed counter 3.

>  /*
>   * We model BTS tracing as another fixed-mode PMC.
>   *
> --
> 2.7.4
>