lists.openwall.net   lists  /  announce  owl-users  owl-dev  john-users  john-dev  passwdqc-users  yescrypt  popa3d-users  /  oss-security  kernel-hardening  musl  sabotage  tlsify  passwords  /  crypt-dev  xvendor  /  Bugtraq  Full-Disclosure  linux-kernel  linux-netdev  linux-ext4  linux-hardening  linux-cve-announce  PHC 
Open Source and information security mailing list archives
 
Hash Suite: Windows password security audit tool. GUI, reports in PDF.
[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]
Date:   Mon, 28 Mar 2022 11:38:00 +0200
From:   Krzysztof Kozlowski <krzk@...nel.org>
To:     wangseok.lee@...sung.com,
        "robh+dt@...nel.org" <robh+dt@...nel.org>,
        "krzk+dt@...nel.org" <krzk+dt@...nel.org>,
        "kishon@...com" <kishon@...com>,
        "vkoul@...nel.org" <vkoul@...nel.org>,
        "linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
        "jesper.nilsson@...s.com" <jesper.nilsson@...s.com>,
        "lars.persson@...s.com" <lars.persson@...s.com>
Cc:     "bhelgaas@...gle.com" <bhelgaas@...gle.com>,
        "linux-phy@...ts.infradead.org" <linux-phy@...ts.infradead.org>,
        "linux-pci@...r.kernel.org" <linux-pci@...r.kernel.org>,
        "devicetree@...r.kernel.org" <devicetree@...r.kernel.org>,
        "lorenzo.pieralisi@....com" <lorenzo.pieralisi@....com>,
        "kw@...ux.com" <kw@...ux.com>,
        "linux-arm-kernel@...s.com" <linux-arm-kernel@...s.com>,
        "kernel@...s.com" <kernel@...s.com>,
        전문기 <moonki.jun@...sung.com>
Subject: Re: [PATCH 0/5] Add support for Axis, ARTPEC-8 PCIe driver

On 28/03/2022 11:02, 이왕석 wrote:
>> --------- Original Message ---------
>> Sender : Krzysztof Kozlowski <krzk@...nel.org>
>> Date : 2022-03-28 16:12 (GMT+9)
>> Title : Re: [PATCH 0/5] Add support for Axis, ARTPEC-8 PCIe driver
>>
>> On 28/03/2022 03:44, 이왕석 wrote:
>>>  This series patches include newly PCIe support for Axis ARTPEC-8 SoC.
>>>  ARTPEC-8 is the SoC platform of Axis Communications.
>>>  PCIe controller driver and phy driver have been newly added.
>>>  There is also a new MAINTAINER in the addition of phy driver.
>>>  PCIe controller is designed based on Design-Ware PCIe controller IP
>>>  and PCIe phy is desinged based on SAMSUNG PHY IP.
>>>  It also includes modifications to the Design-Ware controller driver to 
>>>  run the 64bit-based ARTPEC-8 PCIe controller driver.
>>>  It consists of 6 patches in total.
>>>  
>>>  This series has been tested on AXIS SW bring-up board 
>>>  with ARTPEC-8 chipset.
>>
>> You lost mail threading. This makes reading this difficult for us. Plus
>> you sent something non-applicable (patch #2), so please resend.
>>
>> Knowing recent Samsung reluctance to extend existing drivers and always
>> duplicate, please provide description/analysis why this driver cannot be
>> combined with existing driver. The answer like: we need several syscon
>> because we do not implement other frameworks (like interconnect) are not
>> valid.
>>
>> Best regards,
>> Krzysztof
> 
> Hello, Krzysztof
> Thanks for your review.
> 
> patch#2 was sent to the wrong format so sent again.
> Sorry for causing confusion.

The first sending was HTML. Second was broken text, so still not working.

Please resend everything with proper threading.


> This patch is specialized in Artpec-8, 
> the SoC Platform of Axis Communication, and is newly applied.
> Since the target SoC platform is different from the driver previously 
> used by Samsung, it is difficult to merge with the existing driver.

Recently I always saw such answers and sometimes it was true, sometimes
not. What is exactly different?

Best regards,
Krzysztof

Powered by blists - more mailing lists

Powered by Openwall GNU/*/Linux Powered by OpenVZ