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Message-ID: <20220331103913.2vlneq6clnheuty6@pengutronix.de>
Date:   Thu, 31 Mar 2022 12:39:13 +0200
From:   Marc Kleine-Budde <mkl@...gutronix.de>
To:     Aurelien Jarno <aurelien@...el32.net>
Cc:     linux-kernel@...r.kernel.org, stable@...r.kernel.org,
        Kito Cheng <kito.cheng@...il.com>,
        Paul Walmsley <paul.walmsley@...ive.com>,
        Palmer Dabbelt <palmer@...belt.com>,
        Albert Ou <aou@...s.berkeley.edu>,
        "open list:RISC-V ARCHITECTURE" <linux-riscv@...ts.infradead.org>
Subject: Re: [PATCH] riscv: fix build with binutils 2.38

On 31.03.2022 12:32:47, Marc Kleine-Budde wrote:
> On 26.01.2022 18:14:42, Aurelien Jarno wrote:
> > From version 2.38, binutils default to ISA spec version 20191213. This
> > means that the csr read/write (csrr*/csrw*) instructions and fence.i
> > instruction has separated from the `I` extension, become two standalone
> > extensions: Zicsr and Zifencei. As the kernel uses those instruction,
> > this causes the following build failure:
> > 
> >   CC      arch/riscv/kernel/vdso/vgettimeofday.o
> >   <<BUILDDIR>>/arch/riscv/include/asm/vdso/gettimeofday.h: Assembler messages:
> >   <<BUILDDIR>>/arch/riscv/include/asm/vdso/gettimeofday.h:71: Error: unrecognized opcode `csrr a5,0xc01'
> >   <<BUILDDIR>>/arch/riscv/include/asm/vdso/gettimeofday.h:71: Error: unrecognized opcode `csrr a5,0xc01'
> >   <<BUILDDIR>>/arch/riscv/include/asm/vdso/gettimeofday.h:71: Error: unrecognized opcode `csrr a5,0xc01'
> >   <<BUILDDIR>>/arch/riscv/include/asm/vdso/gettimeofday.h:71: Error: unrecognized opcode `csrr a5,0xc01'
> > 
> > The fix is to specify those extensions explicitely in -march. However as
> > older binutils version do not support this, we first need to detect
> > that.
> > 
> > Cc: stable@...r.kernel.org # 4.15+
> > Cc: Kito Cheng <kito.cheng@...il.com>
> > Signed-off-by: Aurelien Jarno <aurelien@...el32.net>
> > ---
> >  arch/riscv/Makefile | 6 ++++++
> >  1 file changed, 6 insertions(+)
> > 
> > diff --git a/arch/riscv/Makefile b/arch/riscv/Makefile
> > index 8a107ed18b0d..7d81102cffd4 100644
> > --- a/arch/riscv/Makefile
> > +++ b/arch/riscv/Makefile
> > @@ -50,6 +50,12 @@ riscv-march-$(CONFIG_ARCH_RV32I)	:= rv32ima
> >  riscv-march-$(CONFIG_ARCH_RV64I)	:= rv64ima
> >  riscv-march-$(CONFIG_FPU)		:= $(riscv-march-y)fd
> >  riscv-march-$(CONFIG_RISCV_ISA_C)	:= $(riscv-march-y)c
> > +
> > +# Newer binutils versions default to ISA spec version 20191213 which moves some
> > +# instructions from the I extension to the Zicsr and Zifencei extensions.
> > +toolchain-need-zicsr-zifencei := $(call cc-option-yn, -march=$(riscv-march-y)_zicsr_zifencei)
> > +riscv-march-$(toolchain-need-zicsr-zifencei) := $(riscv-march-y)_zicsr_zifencei
> > +
> >  KBUILD_CFLAGS += -march=$(subst fd,,$(riscv-march-y))
> >  KBUILD_AFLAGS += -march=$(riscv-march-y)
> 
> I'm on current linus/master, this change breaks on current Debian
> testing with:
> 
> | make: Leaving directory 'linux'
> |   SYNC    include/config/auto.conf.cmd
> |   GEN     Makefile
> |   GEN     Makefile
> |   CC      scripts/mod/empty.o
> |   CHECK   linux/scripts/mod/empty.c
      ^^^^^
It's actually "sparse" that breaks
      
> | invalid argument to '-march': '_zicsr_zifencei'

| $ sparse --version
| 0.6.4 (Debian: 0.6.4-2)

Compiling without "C=1" for now.

regards,
Marc

-- 
Pengutronix e.K.                 | Marc Kleine-Budde           |
Embedded Linux                   | https://www.pengutronix.de  |
Vertretung West/Dortmund         | Phone: +49-231-2826-924     |
Amtsgericht Hildesheim, HRA 2686 | Fax:   +49-5121-206917-5555 |

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