[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]
Message-ID: <CAE-0n53BBzgU6AJ70JNUBBkDZ1c9ZmpX8ZXLcxLxmmg1=UnSLw@mail.gmail.com>
Date: Fri, 1 Apr 2022 17:09:58 -0500
From: Stephen Boyd <swboyd@...omium.org>
To: Shaik Sajida Bhanu <quic_c_sbhanu@...cinc.com>, agross@...nel.org,
bjorn.andersson@...aro.org, devicetree@...r.kernel.org,
krzk+dt@...nel.org, linux-arm-msm@...r.kernel.org,
linux-kernel@...r.kernel.org, linux-mmc@...r.kernel.org,
robh+dt@...nel.org, ulf.hansson@...aro.org
Cc: quic_rampraka@...cinc.com, quic_pragalla@...cinc.com,
quic_sartgarg@...cinc.com, quic_nitirawa@...cinc.com,
quic_sayalil@...cinc.com
Subject: Re: [PATCH V3 2/2] arm64: dts: qcom: sc7280: Add reset entries for
SDCC controllers
Quoting Shaik Sajida Bhanu (2022-03-17 08:49:25)
> Add gcc hardware reset entries for eMMC and SD card.
>
> Signed-off-by: Shaik Sajida Bhanu <quic_c_sbhanu@...cinc.com>
> ---
> arch/arm64/boot/dts/qcom/sc7280.dtsi | 8 ++++++++
> 1 file changed, 8 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi
> index c07765d..cd50ea3 100644
> --- a/arch/arm64/boot/dts/qcom/sc7280.dtsi
> +++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi
> @@ -881,6 +881,10 @@
> mmc-hs400-1_8v;
> mmc-hs400-enhanced-strobe;
>
> + /* gcc hardware reset entry for eMMC */
Please don't add this worthless comment.
> + resets = <&gcc GCC_SDCC1_BCR>;
> + reset-names = "core_reset";
A "_reset" postfix is redundant. In fact, reset-names shouldn't even be
required.
> +
> sdhc1_opp_table: opp-table {
> compatible = "operating-points-v2";
>
> @@ -2686,6 +2690,10 @@
>
> qcom,dll-config = <0x0007642c>;
>
> + /* gcc hardware reset entry for SD card */
Please don't add this worthless comment.
> + resets = <&gcc GCC_SDCC2_BCR>;
> + reset-names = "core_reset";
> +
> sdhc2_opp_table: opp-table {
> compatible = "operating-points-v2";
>
Powered by blists - more mailing lists