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Message-ID: <7cdc2103-c6d4-e1b6-9804-6739112eee4d@intel.com>
Date: Tue, 5 Apr 2022 08:10:05 -0700
From: Dave Hansen <dave.hansen@...el.com>
To: Peter Zijlstra <peterz@...radead.org>,
Wyes Karny <wyes.karny@....com>
Cc: linux-kernel@...r.kernel.org, Lewis.Carroll@....com,
Mario.Limonciello@....com, gautham.shenoy@....com,
Ananth.Narayan@....com, bharata@....com, len.brown@...el.com,
x86@...nel.org, tglx@...utronix.de, mingo@...hat.com, bp@...en8.de,
dave.hansen@...ux.intel.com, hpa@...or.com,
chang.seok.bae@...el.com, keescook@...omium.org, metze@...ba.org,
zhengqi.arch@...edance.com, mark.rutland@....com
Subject: Re: [PATCH] x86: Prefer MWAIT over HALT on AMD processors
On 4/5/22 07:07, Peter Zijlstra wrote:
> On Tue, Apr 05, 2022 at 06:30:21PM +0530, Wyes Karny wrote:
>> +static inline bool early_mwait_supported(const struct cpuinfo_x86 *c)
>> +{
>> + if (c->x86_vendor == X86_VENDOR_INTEL)
>> + return true;
>> +
>> + if (c->x86_vendor == X86_VENDOR_AMD && cpu_has(c, X86_FEATURE_ZEN))
> What about Hygon? For some reason you guys don't co-ordinate and we end
> up getting endless 'make-same' patches, sometimes separated by years :/
Believe it or not Hygon seems to work OK with this because:
> static void init_hygon(struct cpuinfo_x86 *c)
> {
...
> set_cpu_cap(c, X86_FEATURE_ZEN);
I do worry a bit though that using X86_FEATURE_ZEN is going to bite us
long-term. It currently claims to be set for "family 0x17 or above":
> #define X86_FEATURE_ZEN ( 7*32+28) /* "" CPU is AMD family 0x17 or above (Zen) */
But then it goes and gets used in side-channel defense:
> if (!static_cpu_has(X86_FEATURE_ZEN)) {
> msr |= ssbd_tif_to_amd_ls_cfg(tifn);
> wrmsrl(MSR_AMD64_LS_CFG, msr);
> return;
> }
This seem _bit_ at odds with the commit message (and the AMD SSBD
whitepaper):
> Add the necessary synchronization logic for AMD family 17H.
So, is X86_FEATURE_ZEN for family==0x17, or family>=0x17?
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