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Message-ID: <BL1PR12MB515745615F4C92627033CD5BE2E49@BL1PR12MB5157.namprd12.prod.outlook.com>
Date:   Tue, 5 Apr 2022 15:34:23 +0000
From:   "Limonciello, Mario" <Mario.Limonciello@....com>
To:     Dave Hansen <dave.hansen@...el.com>,
        Peter Zijlstra <peterz@...radead.org>,
        "Karny, Wyes" <Wyes.Karny@....com>
CC:     "linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
        "Carroll, Lewis" <Lewis.Carroll@....com>,
        "Shenoy, Gautham Ranjal" <gautham.shenoy@....com>,
        "Narayan, Ananth" <Ananth.Narayan@....com>,
        "Rao, Bharata Bhasker" <bharata@....com>,
        "len.brown@...el.com" <len.brown@...el.com>,
        "x86@...nel.org" <x86@...nel.org>,
        "tglx@...utronix.de" <tglx@...utronix.de>,
        "mingo@...hat.com" <mingo@...hat.com>,
        "bp@...en8.de" <bp@...en8.de>,
        "dave.hansen@...ux.intel.com" <dave.hansen@...ux.intel.com>,
        "hpa@...or.com" <hpa@...or.com>,
        "chang.seok.bae@...el.com" <chang.seok.bae@...el.com>,
        "keescook@...omium.org" <keescook@...omium.org>,
        "metze@...ba.org" <metze@...ba.org>,
        "zhengqi.arch@...edance.com" <zhengqi.arch@...edance.com>,
        "mark.rutland@....com" <mark.rutland@....com>
Subject: RE: [PATCH] x86: Prefer MWAIT over HALT on AMD processors

[Public]



> -----Original Message-----
> From: Dave Hansen <dave.hansen@...el.com>
> Sent: Tuesday, April 5, 2022 10:10
> To: Peter Zijlstra <peterz@...radead.org>; Karny, Wyes
> <Wyes.Karny@....com>
> Cc: linux-kernel@...r.kernel.org; Carroll, Lewis <Lewis.Carroll@....com>;
> Limonciello, Mario <Mario.Limonciello@....com>; Shenoy, Gautham Ranjal
> <gautham.shenoy@....com>; Narayan, Ananth
> <Ananth.Narayan@....com>; Rao, Bharata Bhasker <bharata@....com>;
> len.brown@...el.com; x86@...nel.org; tglx@...utronix.de;
> mingo@...hat.com; bp@...en8.de; dave.hansen@...ux.intel.com;
> hpa@...or.com; chang.seok.bae@...el.com; keescook@...omium.org;
> metze@...ba.org; zhengqi.arch@...edance.com; mark.rutland@....com
> Subject: Re: [PATCH] x86: Prefer MWAIT over HALT on AMD processors
> 
> On 4/5/22 07:07, Peter Zijlstra wrote:
> > On Tue, Apr 05, 2022 at 06:30:21PM +0530, Wyes Karny wrote:
> >> +static inline bool early_mwait_supported(const struct cpuinfo_x86 *c)
> >> +{
> >> +	if (c->x86_vendor == X86_VENDOR_INTEL)
> >> +		return true;
> >> +
> >> +	if (c->x86_vendor == X86_VENDOR_AMD && cpu_has(c,
> X86_FEATURE_ZEN))
> > What about Hygon? For some reason you guys don't co-ordinate and we
> end
> > up getting endless 'make-same' patches, sometimes separated by years :/
> 
> Believe it or not Hygon seems to work OK with this because:
> 
> > static void init_hygon(struct cpuinfo_x86 *c)
> > {
> ...
> >         set_cpu_cap(c, X86_FEATURE_ZEN);
> 
> I do worry a bit though that using X86_FEATURE_ZEN is going to bite us
> long-term.  It currently claims to be set for "family 0x17 or above":
> 
> > #define X86_FEATURE_ZEN                 ( 7*32+28) /* "" CPU is AMD family
> 0x17 or above (Zen) */
> 
> But then it goes and gets used in side-channel defense:
> 
> >         if (!static_cpu_has(X86_FEATURE_ZEN)) {
> >                 msr |= ssbd_tif_to_amd_ls_cfg(tifn);
> >                 wrmsrl(MSR_AMD64_LS_CFG, msr);
> >                 return;
> >         }
> 
> This seem _bit_ at odds with the commit message (and the AMD SSBD
> whitepaper):
> 
> >     Add the necessary synchronization logic for AMD family 17H.
> 
> So, is X86_FEATURE_ZEN for family==0x17, or family>=0x17?

There are Zen family CPUs and APUs from family 0x19.  Perhaps at the
time of the whitepaper there weren't yet though.

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