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Message-ID: <5873a444-bb32-f0d5-27f1-173f469baf21@intel.com>
Date: Tue, 5 Apr 2022 08:47:20 -0700
From: Dave Hansen <dave.hansen@...el.com>
To: "Limonciello, Mario" <Mario.Limonciello@....com>,
Peter Zijlstra <peterz@...radead.org>,
"Karny, Wyes" <Wyes.Karny@....com>
Cc: "linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
"Carroll, Lewis" <Lewis.Carroll@....com>,
"Shenoy, Gautham Ranjal" <gautham.shenoy@....com>,
"Narayan, Ananth" <Ananth.Narayan@....com>,
"Rao, Bharata Bhasker" <bharata@....com>,
"len.brown@...el.com" <len.brown@...el.com>,
"x86@...nel.org" <x86@...nel.org>,
"tglx@...utronix.de" <tglx@...utronix.de>,
"mingo@...hat.com" <mingo@...hat.com>,
"bp@...en8.de" <bp@...en8.de>,
"dave.hansen@...ux.intel.com" <dave.hansen@...ux.intel.com>,
"hpa@...or.com" <hpa@...or.com>,
"chang.seok.bae@...el.com" <chang.seok.bae@...el.com>,
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"metze@...ba.org" <metze@...ba.org>,
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Subject: Re: [PATCH] x86: Prefer MWAIT over HALT on AMD processors
On 4/5/22 08:34, Limonciello, Mario wrote:
>>> if (!static_cpu_has(X86_FEATURE_ZEN)) {
>>> msr |= ssbd_tif_to_amd_ls_cfg(tifn);
>>> wrmsrl(MSR_AMD64_LS_CFG, msr);
>>> return;
>>> }
>> This seem _bit_ at odds with the commit message (and the AMD SSBD
>> whitepaper):
>>
>>> Add the necessary synchronization logic for AMD family 17H.
>> So, is X86_FEATURE_ZEN for family==0x17, or family>=0x17?
> There are Zen family CPUs and APUs from family 0x19. Perhaps at the
> time of the whitepaper there weren't yet though.
Is this a gap in the documentation, then? Is there some documentation
of the availability of SSBD mitigations on family 0x19?
Anyway, back to MWAIT... It would be really great to include the
assumptions about what X86_FEATURE_ZEN means in the context of this
patch. Does this patch *really* mean "Zen microarchitecture" only?
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