linux-kernel - RE: [PATCH] x86: Prefer MWAIT over HALT on AMD processors

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Message-ID: <BL1PR12MB515702C06E483DF4EB78A7ADE2E49@BL1PR12MB5157.namprd12.prod.outlook.com>
Date:   Tue, 5 Apr 2022 20:40:16 +0000
From:   "Limonciello, Mario" <Mario.Limonciello@....com>
To:     Dave Hansen <dave.hansen@...el.com>,
        Peter Zijlstra <peterz@...radead.org>,
        "Karny, Wyes" <Wyes.Karny@....com>
CC:     "linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
        "Carroll, Lewis" <Lewis.Carroll@....com>,
        "Shenoy, Gautham Ranjal" <gautham.shenoy@....com>,
        "Narayan, Ananth" <Ananth.Narayan@....com>,
        "Rao, Bharata Bhasker" <bharata@....com>,
        "len.brown@...el.com" <len.brown@...el.com>,
        "x86@...nel.org" <x86@...nel.org>,
        "tglx@...utronix.de" <tglx@...utronix.de>,
        "mingo@...hat.com" <mingo@...hat.com>,
        "bp@...en8.de" <bp@...en8.de>,
        "dave.hansen@...ux.intel.com" <dave.hansen@...ux.intel.com>,
        "hpa@...or.com" <hpa@...or.com>,
        "chang.seok.bae@...el.com" <chang.seok.bae@...el.com>,
        "keescook@...omium.org" <keescook@...omium.org>,
        "metze@...ba.org" <metze@...ba.org>,
        "zhengqi.arch@...edance.com" <zhengqi.arch@...edance.com>,
        "mark.rutland@....com" <mark.rutland@....com>
Subject: RE: [PATCH] x86: Prefer MWAIT over HALT on AMD processors

[Public]



> -----Original Message-----
> From: Dave Hansen <dave.hansen@...el.com>
> Sent: Tuesday, April 5, 2022 10:47
> To: Limonciello, Mario <Mario.Limonciello@....com>; Peter Zijlstra
> <peterz@...radead.org>; Karny, Wyes <Wyes.Karny@....com>
> Cc: linux-kernel@...r.kernel.org; Carroll, Lewis <Lewis.Carroll@....com>;
> Shenoy, Gautham Ranjal <gautham.shenoy@....com>; Narayan, Ananth
> <Ananth.Narayan@....com>; Rao, Bharata Bhasker <bharata@....com>;
> len.brown@...el.com; x86@...nel.org; tglx@...utronix.de;
> mingo@...hat.com; bp@...en8.de; dave.hansen@...ux.intel.com;
> hpa@...or.com; chang.seok.bae@...el.com; keescook@...omium.org;
> metze@...ba.org; zhengqi.arch@...edance.com; mark.rutland@....com
> Subject: Re: [PATCH] x86: Prefer MWAIT over HALT on AMD processors
> 
> On 4/5/22 08:34, Limonciello, Mario wrote:
> >>>         if (!static_cpu_has(X86_FEATURE_ZEN)) {
> >>>                 msr |= ssbd_tif_to_amd_ls_cfg(tifn);
> >>>                 wrmsrl(MSR_AMD64_LS_CFG, msr);
> >>>                 return;
> >>>         }
> >> This seem _bit_ at odds with the commit message (and the AMD SSBD
> >> whitepaper):
> >>
> >>>     Add the necessary synchronization logic for AMD family 17H.
> >> So, is X86_FEATURE_ZEN for family==0x17, or family>=0x17?
> > There are Zen family CPUs and APUs from family 0x19.  Perhaps at the
> > time of the whitepaper there weren't yet though.
> 
> Is this a gap in the documentation, then?  Is there some documentation
> of the availability of SSBD mitigations on family 0x19?

It looks like a misinterpretation of the document.

Notice it mentions in Non-architectural MSRs explicitly:

"some models of family 17h have logic that allow loads to bypass older stores 
but lack the architectural SPEC_CTRL or VIRT_SPEC_CTR"

But that is not for all family 17h nor for family 19h.  You can see earlier in
the document the method to detect presence for SSBD which applies to the
rest of 17h and 19h.  That code in amd_set_core_ssb_state is only used for
one of the mitigation codepaths without MSR support, not for all Zen CPUs.

> 
> Anyway, back to MWAIT...  It would be really great to include the
> assumptions about what X86_FEATURE_ZEN means in the context of this
> patch.  Does this patch *really* mean "Zen microarchitecture" only?