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Message-ID: <Yk1dvBS4BPCPYt+t@zn.tnic>
Date: Wed, 6 Apr 2022 11:30:36 +0200
From: Borislav Petkov <bp@...en8.de>
To: "Carroll, Lewis" <Lewis.Carroll@....com>
Cc: "linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
"peterz@...radead.org" <peterz@...radead.org>,
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"Karny, Wyes" <Wyes.Karny@....com>,
"Limonciello, Mario" <Mario.Limonciello@....com>,
"Shenoy, Gautham Ranjal" <gautham.shenoy@....com>,
"Narayan, Ananth" <Ananth.Narayan@....com>,
"Rao, Bharata Bhasker" <bharata@....com>,
"len.brown@...el.com" <len.brown@...el.com>,
"x86@...nel.org" <x86@...nel.org>,
"tglx@...utronix.de" <tglx@...utronix.de>,
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Subject: Re: [PATCH] x86: Prefer MWAIT over HALT on AMD processors
On Tue, Apr 05, 2022 at 09:49:27PM +0000, Carroll, Lewis wrote:
> Just when I thought I was being thorough. Any of the above will block the
> cpuidle driver from loading. As will absence of _CST ACPI methods (add that
> as a fourth cause).
Yah, put that all in the text over prefer_mwait_c1_over_halt() pls.
> We will have to see what we can sanitize. The original performance observation
> (packet loss in a networking application) led to discovery of lots of cycles
> in the various go-to-sleep-via-halt and wake-from-halt-via-IPI functions. Wyes
> collected the raw data on the relative idle+wake-up latency and included that
> in the commit msg. Think of that delta as the root cause of the performance
> regression in this case.
You don't have to write novels - just leave enough breadcrumbs so that
people looking at this in the future know *why* this was done.
> Yes we are saying use MWAIT instead of HLT on all known (as of today) Zen
> uarch CPUs (AMD >= 17h and Hygon).
Wyes in his reply from today says that the logic is not that simple so
you folks need to define clearly which cases are we talking about here:
Zen uarch, MWAIT CPUID bit set/clear, MONITOR bug, <other feature bits>,
etc.
Thx.
--
Regards/Gruss,
Boris.
https://people.kernel.org/tglx/notes-about-netiquette
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