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Message-ID: <6769ea2d-9e6a-03b1-0e05-cb5b7379cb5e@linaro.org>
Date: Thu, 7 Apr 2022 20:52:34 +0200
From: Krzysztof Kozlowski <krzysztof.kozlowski@...aro.org>
To: Brad Larson <brad@...sando.io>,
linux-arm-kernel@...ts.infradead.org
Cc: arnd@...db.de, linus.walleij@...aro.org, bgolaszewski@...libre.com,
broonie@...nel.org, fancer.lancer@...il.com,
adrian.hunter@...el.com, ulf.hansson@...aro.org, olof@...om.net,
dac2@...sando.io, linux-gpio@...r.kernel.org,
linux-spi@...r.kernel.org, linux-mmc@...r.kernel.org,
devicetree@...r.kernel.org, linux-kernel@...r.kernel.org
Subject: Re: [PATCH 05/11] dt-bindings: spi: dw: Add Pensando Elba SoC SPI
Controller bindings
On 07/04/2022 01:36, Brad Larson wrote:
> The Pensando Elba SoC has integrated the DW APB SPI Controller
> and requires the property pensando,syscon-spics for access
> to the spics control register.
>
> Signed-off-by: Brad Larson <brad@...sando.io>
> ---
> Change from V3:
> - Add required property pensando,syscon-spics to go with
> pensando,elba-spi
Thank you for your patch. There is something to discuss/improve.
> .../bindings/spi/snps,dw-apb-ssi.yaml | 17 +++++++++++++++++
> 1 file changed, 17 insertions(+)
>
> diff --git a/Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.yaml b/Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.yaml
> index d7e08b03e204..41c3bbf5a55c 100644
> --- a/Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.yaml
> +++ b/Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.yaml
> @@ -37,6 +37,21 @@ allOf:
> else:
> required:
> - interrupts
> + - if:
> + properties:
> + compatible:
> + contains:
> + enum:
> + - pensando,elba-spi
> + then:
> + properties:
> + pensando,syscon-spics:
> + $ref: /schemas/types.yaml#/definitions/phandle
> + description:
> + Phandle to the system control device node which provides access to
> + the spics control register
It looks you only need to poke one register from spics, so it could be
something like:
items:
- items:
- description: Phandle to the system control device node
- description: spics control register offset
Best regards,
Krzysztof
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