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Message-ID: <26951c45-f742-2f0e-f4a6-281a031c3471@gmail.com>
Date: Thu, 7 Apr 2022 08:21:29 +0200
From: Christian König <ckoenig.leichtzumerken@...il.com>
To: Grigory Vasilyev <h0tc0d3@...il.com>,
Rodrigo Siqueira <Rodrigo.Siqueira@....com>,
Melissa Wen <mwen@...lia.com>
Cc: Joseph Greathouse <Joseph.Greathouse@....com>,
Guchun Chen <guchun.chen@....com>,
"Pan, Xinhui" <Xinhui.Pan@....com>, linux-kernel@...r.kernel.org,
amd-gfx@...ts.freedesktop.org, David Airlie <airlied@...ux.ie>,
dri-devel@...ts.freedesktop.org, Daniel Vetter <daniel@...ll.ch>,
Alex Deucher <alexander.deucher@....com>,
Evan Quan <evan.quan@....com>,
Christian König <christian.koenig@....com>
Subject: Re: [PATCH] drm/amdgpu: Fix code with incorrect enum type
Am 06.04.22 um 18:50 schrieb Grigory Vasilyev:
> Instead of the 'amdgpu_ring_priority_level' type,
> the 'amdgpu_gfx_pipe_priority' type was used,
> which is an error when setting ring priority.
> This is a minor error, but may cause problems in the future.
>
> Instead of AMDGPU_RING_PRIO_2 = 2, we can use AMDGPU_RING_PRIO_MAX = 3,
> but AMDGPU_RING_PRIO_2 = 2 is used for compatibility with
> AMDGPU_GFX_PIPE_PRIO_HIGH = 2, and not change the behavior of the
> code.
>
> Signed-off-by: Grigory Vasilyev <h0tc0d3@...il.com>
Good catch, Acked-by: Christian König <christian.koenig@....com>
> ---
> drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
> index 5554084ec1f1..9bc26395f833 100644
> --- a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
> @@ -1929,7 +1929,7 @@ static int gfx_v8_0_compute_ring_init(struct amdgpu_device *adev, int ring_id,
> + ring->pipe;
>
> hw_prio = amdgpu_gfx_is_high_priority_compute_queue(adev, ring) ?
> - AMDGPU_GFX_PIPE_PRIO_HIGH : AMDGPU_RING_PRIO_DEFAULT;
> + AMDGPU_RING_PRIO_2 : AMDGPU_RING_PRIO_DEFAULT;
> /* type-2 packets are deprecated on MEC, use type-3 instead */
> r = amdgpu_ring_init(adev, ring, 1024, &adev->gfx.eop_irq, irq_type,
> hw_prio, NULL);
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