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Message-Id: <1649759528-15125-3-git-send-email-quic_c_sbhanu@quicinc.com>
Date:   Tue, 12 Apr 2022 16:02:08 +0530
From:   Shaik Sajida Bhanu <quic_c_sbhanu@...cinc.com>
To:     ulf.hansson@...aro.org, robh+dt@...nel.org, krzk+dt@...nel.org,
        linux-mmc@...r.kernel.org, devicetree@...r.kernel.org,
        linux-kernel@...r.kernel.org, agross@...nel.org,
        bjorn.andersson@...aro.org, linux-arm-msm@...r.kernel.org
Cc:     quic_rampraka@...cinc.com, quic_pragalla@...cinc.com,
        quic_sartgarg@...cinc.com, quic_nitirawa@...cinc.com,
        quic_sayalil@...cinc.com,
        Shaik Sajida Bhanu <quic_c_sbhanu@...cinc.com>
Subject: [PATCH V4 2/2] arm64: dts: qcom: sc7280: Add reset entries for SDCC controllers

Add gcc hardware reset entries for eMMC and SD card.

Signed-off-by: Shaik Sajida Bhanu <quic_c_sbhanu@...cinc.com>
---
 arch/arm64/boot/dts/qcom/sc7280.dtsi | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi
index f0b64be..e2393d1 100644
--- a/arch/arm64/boot/dts/qcom/sc7280.dtsi
+++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi
@@ -881,6 +881,8 @@
 			mmc-hs400-1_8v;
 			mmc-hs400-enhanced-strobe;
 
+			resets = <&gcc GCC_SDCC1_BCR>;
+
 			sdhc1_opp_table: opp-table {
 				compatible = "operating-points-v2";
 
@@ -2686,6 +2688,8 @@
 
 			qcom,dll-config = <0x0007642c>;
 
+			resets = <&gcc GCC_SDCC2_BCR>;
+
 			sdhc2_opp_table: opp-table {
 				compatible = "operating-points-v2";
 
-- 
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