linux-kernel - Re: [PATCH V4 1/2] dt-bindings: mmc: sdhci-msm: Add gcc resets strings

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Message-ID: <CAPDyKFrJDVBdyu4=0dXaBs8FhsF5jvcLKGgfjjbB-rVztxmgqg@mail.gmail.com>
Date:   Tue, 12 Apr 2022 16:18:40 +0200
From:   Ulf Hansson <ulf.hansson@...aro.org>
To:     Shaik Sajida Bhanu <quic_c_sbhanu@...cinc.com>
Cc:     robh+dt@...nel.org, krzk+dt@...nel.org, linux-mmc@...r.kernel.org,
        devicetree@...r.kernel.org, linux-kernel@...r.kernel.org,
        agross@...nel.org, bjorn.andersson@...aro.org,
        linux-arm-msm@...r.kernel.org, quic_rampraka@...cinc.com,
        quic_pragalla@...cinc.com, quic_sartgarg@...cinc.com,
        quic_nitirawa@...cinc.com, quic_sayalil@...cinc.com,
        Bhupesh Sharma <bhupesh.sharma@...aro.org>
Subject: Re: [PATCH V4 1/2] dt-bindings: mmc: sdhci-msm: Add gcc resets strings

+ Bhupesh

On Tue, 12 Apr 2022 at 12:33, Shaik Sajida Bhanu
<quic_c_sbhanu@...cinc.com> wrote:
>
> Add gcc hardware reset supported strings for qcom-sdhci controller.
>
> Signed-off-by: Shaik Sajida Bhanu <quic_c_sbhanu@...cinc.com>

As stated earlier, I would really like to see the binding being
converted to the yaml format first. It seems like Bhupesh is working
on the conversion [1].

Kind regards
Uffe

[1]
https://www.spinics.net/lists/linux-arm-msm/msg107809.html


> ---
>  Documentation/devicetree/bindings/mmc/sdhci-msm.txt | 5 +++++
>  1 file changed, 5 insertions(+)
>
> diff --git a/Documentation/devicetree/bindings/mmc/sdhci-msm.txt b/Documentation/devicetree/bindings/mmc/sdhci-msm.txt
> index 6216ed7..9f02461 100644
> --- a/Documentation/devicetree/bindings/mmc/sdhci-msm.txt
> +++ b/Documentation/devicetree/bindings/mmc/sdhci-msm.txt
> @@ -76,6 +76,7 @@ Optional Properties:
>                 "cpu-sdhc".
>                 Please refer to Documentation/devicetree/bindings/
>                 interconnect/ for more details.
> +- resets: Phandle and reset specifier for the device's reset.
>
>  Example:
>
> @@ -98,6 +99,8 @@ Example:
>                                 <&qnoc MASTER_CPU_ID &qnoc SLAVE_SDCC_ID>;
>                 interconnect-names = "sdhc-ddr","cpu-sdhc";
>
> +               resets = <&gcc GCC_SDCC1_BCR>;
> +
>                 qcom,dll-config = <0x000f642c>;
>                 qcom,ddr-config = <0x80040868>;
>         };
> @@ -118,6 +121,8 @@ Example:
>                 clocks = <&gcc GCC_SDCC2_APPS_CLK>, <&gcc GCC_SDCC2_AHB_CLK>;
>                 clock-names = "core", "iface";
>
> +               resets = <&gcc GCC_SDCC2_BCR>;
> +
>                 qcom,dll-config = <0x0007642c>;
>                 qcom,ddr-config = <0x80040868>;
>         };
> --
> QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member
> of Code Aurora Forum, hosted by The Linux Foundation
>