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Date: Wed, 13 Apr 2022 10:27:19 +0300
From: Dmitry Baryshkov <dmitry.baryshkov@...aro.org>
To: Bhupesh Sharma <bhupesh.sharma@...aro.org>,
linux-phy@...ts.infradead.org
Cc: bhupesh.linux@...il.com, linux-arm-msm@...r.kernel.org,
linux-kernel@...r.kernel.org, vkoul@...nel.org,
bjorn.andersson@...aro.org
Subject: Re: [PATCH v4 2/2] phy: qcom-qmp: Add SM8150 PCIe QMP PHYs
On 26/03/2022 01:21, Bhupesh Sharma wrote:
> SM8150 has multiple (different) PHY versions:
> QMP GEN3x1 PHY - 1 lane
> QMP GEN3x2 PHY - 2 lanes
>
> Add support for these with relevant init sequence.
>
> Cc: Bjorn Andersson <bjorn.andersson@...aro.org>
> Cc: Vinod Koul <vkoul@...nel.org>
> Signed-off-by: Bhupesh Sharma <bhupesh.sharma@...aro.org>
> ---
> drivers/phy/qualcomm/phy-qcom-qmp.c | 90 +++++++++++++++++++++++++++++
> 1 file changed, 90 insertions(+)
>
> diff --git a/drivers/phy/qualcomm/phy-qcom-qmp.c b/drivers/phy/qualcomm/phy-qcom-qmp.c
> index b144ae1f729a..8e928b9619b6 100644
> --- a/drivers/phy/qualcomm/phy-qcom-qmp.c
> +++ b/drivers/phy/qualcomm/phy-qcom-qmp.c
> @@ -3294,6 +3294,11 @@ static const char * const sdm845_pciephy_clk_l[] = {
> "aux", "cfg_ahb", "ref", "refgen",
> };
>
> +/* the pcie phy on sm8150 doesn't have a ref clock */
> +static const char * const sm8150_pciephy_clk_l[] = {
> + "aux", "cfg_ahb", "refgen",
On sm8250 we use GCC_WIFI/WIGIG/MDM_CLKREF_EN clocks as "ref".
Downstream dts lists them as "pcie_X_ldo". sm8150 also has these clocks
(GCC_PCIE_n_CLKREF_CLK). Is there any reason why we use CLKREF clocks on
sm8250, but ommit them on sm8150?
> +};
> +
> static const char * const qmp_v4_phy_clk_l[] = {
> "aux", "ref_clk_src", "ref", "com_aux",
> };
> @@ -3583,6 +3588,85 @@ static const struct qmp_phy_cfg sdm845_qhp_pciephy_cfg = {
> .pwrdn_delay_max = 1005, /* us */
> };
>
> +static const struct qmp_phy_cfg sm8150_qmp_gen3x1_pciephy_cfg = {
> + .type = PHY_TYPE_PCIE,
> + .nlanes = 1,
> +
> + .serdes_tbl = sm8250_qmp_pcie_serdes_tbl,
> + .serdes_tbl_num = ARRAY_SIZE(sm8250_qmp_pcie_serdes_tbl),
> + .serdes_tbl_sec = sm8250_qmp_gen3x1_pcie_serdes_tbl,
> + .serdes_tbl_num_sec = ARRAY_SIZE(sm8250_qmp_gen3x1_pcie_serdes_tbl),
> + .tx_tbl = sm8250_qmp_pcie_tx_tbl,
> + .tx_tbl_num = ARRAY_SIZE(sm8250_qmp_pcie_tx_tbl),
> + .rx_tbl = sm8250_qmp_pcie_rx_tbl,
> + .rx_tbl_num = ARRAY_SIZE(sm8250_qmp_pcie_rx_tbl),
> + .rx_tbl_sec = sm8250_qmp_gen3x1_pcie_rx_tbl,
> + .rx_tbl_num_sec = ARRAY_SIZE(sm8250_qmp_gen3x1_pcie_rx_tbl),
> + .pcs_tbl = sm8250_qmp_pcie_pcs_tbl,
> + .pcs_tbl_num = ARRAY_SIZE(sm8250_qmp_pcie_pcs_tbl),
> + .pcs_tbl_sec = sm8250_qmp_gen3x1_pcie_pcs_tbl,
> + .pcs_tbl_num_sec = ARRAY_SIZE(sm8250_qmp_gen3x1_pcie_pcs_tbl),
> + .pcs_misc_tbl = sm8250_qmp_pcie_pcs_misc_tbl,
> + .pcs_misc_tbl_num = ARRAY_SIZE(sm8250_qmp_pcie_pcs_misc_tbl),
> + .pcs_misc_tbl_sec = sm8250_qmp_gen3x1_pcie_pcs_misc_tbl,
> + .pcs_misc_tbl_num_sec = ARRAY_SIZE(sm8250_qmp_gen3x1_pcie_pcs_misc_tbl),
> + .clk_list = sm8150_pciephy_clk_l,
> + .num_clks = ARRAY_SIZE(sm8150_pciephy_clk_l),
> + .reset_list = sdm845_pciephy_reset_l,
> + .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l),
> + .vreg_list = qmp_phy_vreg_l,
> + .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
> + .regs = sm8250_pcie_regs_layout,
> +
> + .start_ctrl = PCS_START | SERDES_START,
> + .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL,
> + .phy_status = PHYSTATUS,
> +
> + .has_pwrdn_delay = true,
> + .pwrdn_delay_min = 995, /* us */
> + .pwrdn_delay_max = 1005, /* us */
> +};
> +
> +static const struct qmp_phy_cfg sm8150_qmp_gen3x2_pciephy_cfg = {
> + .type = PHY_TYPE_PCIE,
> + .nlanes = 2,
> +
> + .serdes_tbl = sm8250_qmp_pcie_serdes_tbl,
> + .serdes_tbl_num = ARRAY_SIZE(sm8250_qmp_pcie_serdes_tbl),
> + .tx_tbl = sm8250_qmp_pcie_tx_tbl,
> + .tx_tbl_num = ARRAY_SIZE(sm8250_qmp_pcie_tx_tbl),
> + .tx_tbl_sec = sm8250_qmp_gen3x2_pcie_tx_tbl,
> + .tx_tbl_num_sec = ARRAY_SIZE(sm8250_qmp_gen3x2_pcie_tx_tbl),
> + .rx_tbl = sm8250_qmp_pcie_rx_tbl,
> + .rx_tbl_num = ARRAY_SIZE(sm8250_qmp_pcie_rx_tbl),
> + .rx_tbl_sec = sm8250_qmp_gen3x2_pcie_rx_tbl,
> + .rx_tbl_num_sec = ARRAY_SIZE(sm8250_qmp_gen3x2_pcie_rx_tbl),
> + .pcs_tbl = sm8250_qmp_pcie_pcs_tbl,
> + .pcs_tbl_num = ARRAY_SIZE(sm8250_qmp_pcie_pcs_tbl),
> + .pcs_tbl_sec = sm8250_qmp_gen3x2_pcie_pcs_tbl,
> + .pcs_tbl_num_sec = ARRAY_SIZE(sm8250_qmp_gen3x2_pcie_pcs_tbl),
> + .pcs_misc_tbl = sm8250_qmp_pcie_pcs_misc_tbl,
> + .pcs_misc_tbl_num = ARRAY_SIZE(sm8250_qmp_pcie_pcs_misc_tbl),
> + .pcs_misc_tbl_sec = sm8250_qmp_gen3x2_pcie_pcs_misc_tbl,
> + .pcs_misc_tbl_num_sec = ARRAY_SIZE(sm8250_qmp_gen3x2_pcie_pcs_misc_tbl),
> + .clk_list = sm8150_pciephy_clk_l,
> + .num_clks = ARRAY_SIZE(sm8150_pciephy_clk_l),
> + .reset_list = sdm845_pciephy_reset_l,
> + .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l),
> + .vreg_list = qmp_phy_vreg_l,
> + .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
> + .regs = sm8250_pcie_regs_layout,
> +
> + .start_ctrl = PCS_START | SERDES_START,
> + .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL,
> + .phy_status = PHYSTATUS,
> +
> + .is_dual_lane_phy = true,
> + .has_pwrdn_delay = true,
> + .pwrdn_delay_min = 995, /* us */
> + .pwrdn_delay_max = 1005, /* us */
> +};
> +
> static const struct qmp_phy_cfg sm8250_qmp_gen3x1_pciephy_cfg = {
> .type = PHY_TYPE_PCIE,
> .nlanes = 1,
> @@ -6007,6 +6091,12 @@ static const struct of_device_id qcom_qmp_phy_of_match_table[] = {
> }, {
> .compatible = "qcom,sm6115-qmp-ufs-phy",
> .data = &sm6115_ufsphy_cfg,
> + }, {
> + .compatible = "qcom,sm8150-qmp-gen3x1-pcie-phy",
> + .data = &sm8150_qmp_gen3x1_pciephy_cfg,
> + }, {
> + .compatible = "qcom,sm8150-qmp-gen3x2-pcie-phy",
> + .data = &sm8150_qmp_gen3x2_pciephy_cfg,
> }, {
> .compatible = "qcom,sm8150-qmp-ufs-phy",
> .data = &sm8150_ufsphy_cfg,
--
With best wishes
Dmitry
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