lists.openwall.net   lists  /  announce  owl-users  owl-dev  john-users  john-dev  passwdqc-users  yescrypt  popa3d-users  /  oss-security  kernel-hardening  musl  sabotage  tlsify  passwords  /  crypt-dev  xvendor  /  Bugtraq  Full-Disclosure  linux-kernel  linux-netdev  linux-ext4  linux-hardening  linux-cve-announce  PHC 
Open Source and information security mailing list archives
 
Hash Suite: Windows password security audit tool. GUI, reports in PDF.
[<prev] [next>] [<thread-prev] [day] [month] [year] [list]
Date:   Wed, 13 Apr 2022 10:29:32 +0300
From:   Dmitry Baryshkov <dmitry.baryshkov@...aro.org>
To:     Bhupesh Sharma <bhupesh.sharma@...aro.org>,
        linux-phy@...ts.infradead.org
Cc:     bhupesh.linux@...il.com, linux-arm-msm@...r.kernel.org,
        linux-kernel@...r.kernel.org, vkoul@...nel.org,
        bjorn.andersson@...aro.org, Rob Herring <robh@...nel.org>
Subject: Re: [PATCH v4 1/2] dt-bindings: phy: qcom,qmp: Add SM8150 PCIe PHY
 bindings

On 26/03/2022 01:21, Bhupesh Sharma wrote:
> Add the following two PCIe PHYs found on SM8150, to the QMP binding:
> 
> QMP GEN3x1 PHY - 1 lane
> QMP GEN3x2 PHY - 2 lanes
> 
> Acked-by: Rob Herring <robh@...nel.org>
> Signed-off-by: Bhupesh Sharma <bhupesh.sharma@...aro.org>
> ---
>   Documentation/devicetree/bindings/phy/qcom,qmp-phy.yaml | 4 ++++
>   1 file changed, 4 insertions(+)
> 
> diff --git a/Documentation/devicetree/bindings/phy/qcom,qmp-phy.yaml b/Documentation/devicetree/bindings/phy/qcom,qmp-phy.yaml
> index e20d9b087bb8..1e08acb8a59a 100644
> --- a/Documentation/devicetree/bindings/phy/qcom,qmp-phy.yaml
> +++ b/Documentation/devicetree/bindings/phy/qcom,qmp-phy.yaml
> @@ -39,6 +39,8 @@ properties:
>         - qcom,sdm845-qmp-usb3-phy
>         - qcom,sdm845-qmp-usb3-uni-phy
>         - qcom,sm6115-qmp-ufs-phy
> +      - qcom,sm8150-qmp-gen3x1-pcie-phy
> +      - qcom,sm8150-qmp-gen3x2-pcie-phy
>         - qcom,sm8150-qmp-ufs-phy
>         - qcom,sm8150-qmp-usb3-phy
>         - qcom,sm8150-qmp-usb3-uni-phy
> @@ -336,6 +338,8 @@ allOf:
>                 - qcom,sdm845-qhp-pcie-phy
>                 - qcom,sdm845-qmp-pcie-phy
>                 - qcom,sdx55-qmp-pcie-phy
> +              - qcom,sm8150-qmp-gen3x1-pcie-phy
> +              - qcom,sm8150-qmp-gen3x2-pcie-phy

If you add your compatible strings to this block, it means that the dtsi 
will provide 4 clocks (aux, cfg_ahb, ref and refgen). However judging 
from the patch 2 it looks like you don't want to provide ref clock?

>                 - qcom,sm8250-qmp-gen3x1-pcie-phy
>                 - qcom,sm8250-qmp-gen3x2-pcie-phy
>                 - qcom,sm8250-qmp-modem-pcie-phy


-- 
With best wishes
Dmitry

Powered by blists - more mailing lists

Powered by Openwall GNU/*/Linux Powered by OpenVZ