linux-kernel - RE: [PATCH v3 1/4] dt-bindings: pci: layerscape-pci: Add a optional property big-endian

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Message-ID: <AS8PR04MB89460EF821A142C8BF2303588FEF9@AS8PR04MB8946.eurprd04.prod.outlook.com>
Date:   Thu, 14 Apr 2022 20:03:23 +0000
From:   Leo Li <leoyang.li@....com>
To:     Bjorn Helgaas <helgaas@...nel.org>
CC:     Bjorn Helgaas <bhelgaas@...gle.com>,
        "Z.Q. Hou" <zhiqiang.hou@....com>, Rob Herring <robh@...nel.org>,
        "linux-pci@...r.kernel.org" <linux-pci@...r.kernel.org>,
        "devicetree@...r.kernel.org" <devicetree@...r.kernel.org>,
        "linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>
Subject: RE: [PATCH v3 1/4] dt-bindings: pci: layerscape-pci: Add a optional
 property big-endian



> -----Original Message-----
> From: Bjorn Helgaas <helgaas@...nel.org>
> Sent: Thursday, April 14, 2022 2:28 PM
> To: Leo Li <leoyang.li@....com>
> Cc: Bjorn Helgaas <bhelgaas@...gle.com>; Z.Q. Hou
> <zhiqiang.hou@....com>; Rob Herring <robh@...nel.org>; linux-
> pci@...r.kernel.org; devicetree@...r.kernel.org; linux-
> kernel@...r.kernel.org
> Subject: Re: [PATCH v3 1/4] dt-bindings: pci: layerscape-pci: Add a optional
> property big-endian
> 
> On Fri, Mar 11, 2022 at 05:49:35PM -0600, Li Yang wrote:
> > From: Hou Zhiqiang <Zhiqiang.Hou@....com>
> >
> > This property is to indicate the endianness when accessing the PEX_LUT
> > and PF register block, so if these registers are implemented in
> > big-endian, specify this property.
> >
> > Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@....com>
> > Acked-by: Rob Herring <robh@...nel.org>
> > ---
> >  Documentation/devicetree/bindings/pci/layerscape-pci.txt | 4 ++++
> >  1 file changed, 4 insertions(+)
> >
> > diff --git a/Documentation/devicetree/bindings/pci/layerscape-pci.txt
> > b/Documentation/devicetree/bindings/pci/layerscape-pci.txt
> > index f36efa73a470..215d2ee65c83 100644
> > --- a/Documentation/devicetree/bindings/pci/layerscape-pci.txt
> > +++ b/Documentation/devicetree/bindings/pci/layerscape-pci.txt
> > @@ -40,6 +40,10 @@ Required properties:
> >    of the data transferred from/to the IP block. This can avoid the software
> >    cache flush/invalid actions, and improve the performance significantly.
> >
> > +Optional properties:
> > +- big-endian: If the PEX_LUT and PF register block is in big-endian,
> > +specify
> > +  this property.
> 
> What's the purpose of this?  I don't see any code that uses this property.
> 
> I guess this might be related to of_device_is_big_endian()?  I do see some
> code that uses of_device_is_big_endian(), but nothing that looks relevant to
> layerscape in particular.

These two register blocks are not used in basic operation but are needed for the power management support.  There is patch in review from Zhiqiang ("PCI: layerscape: Add power management support") that need to use these registers.

But since this is an intrinsic property of the hardware, I think we should include it in the binding and dtses before the code using it hit the mainline.

> 
> >  Example:
> >
> >  	pcie@...0000 {
> > --
> > 2.25.1
> >