linux-kernel - Re: [PATCH v6 3/4] arm64: dts: rockchip: add rk3568 pcie2x1 controller

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives

Hash Suite: Windows password security audit tool. GUI, reports in PDF.

[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]

Date:   Sat, 16 Apr 2022 06:17:15 -0400
From:   Peter Geis <pgwipeout@...il.com>
To:     Dmitry Osipenko <dmitry.osipenko@...labora.com>
Cc:     Rob Herring <robh+dt@...nel.org>,
        Krzysztof Kozlowski <krzk+dt@...nel.org>,
        Heiko Stuebner <heiko@...ech.de>,
        "open list:ARM/Rockchip SoC..." <linux-rockchip@...ts.infradead.org>,
        PCI <linux-pci@...r.kernel.org>,
        devicetree <devicetree@...r.kernel.org>,
        arm-mail-list <linux-arm-kernel@...ts.infradead.org>,
        Linux Kernel Mailing List <linux-kernel@...r.kernel.org>
Subject: Re: [PATCH v6 3/4] arm64: dts: rockchip: add rk3568 pcie2x1 controller

On Sat, Apr 16, 2022 at 6:08 AM Dmitry Osipenko
<dmitry.osipenko@...labora.com> wrote:
>
> Hi Peter,
>
> On 4/16/22 13:05, Peter Geis wrote:
> > +     pcie2x1: pcie@...60000 {
> > +             compatible = "rockchip,rk3568-pcie";
> > +             #address-cells = <3>;
> > +             #size-cells = <2>;
> > +             bus-range = <0x0 0xf>;
> > +             assigned-clocks = <&cru ACLK_PCIE20_MST>, <&cru ACLK_PCIE20_SLV>,
> > +                      <&cru ACLK_PCIE20_DBI>, <&cru PCLK_PCIE20>,
> > +                      <&cru CLK_PCIE20_AUX_NDFT>;
>
> Why these assigned-clocks are needed? I don't see anything assigned in
> this patchset.

Ah, those are remnants of early bringup when performance wasn't good
and I was manually setting clock rates.