linux-kernel - Re: [PATCH 1/7] clk: mediatek: reset: Correct the logic of setting register

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Message-ID: <CAGXv+5FXTft7-E5LnuZdNo8Tq6OKOKwt58GgJD_+z1N5u6B8yw@mail.gmail.com>
Date:   Tue, 19 Apr 2022 13:48:45 +0800
From:   Chen-Yu Tsai <wenst@...omium.org>
To:     Rex-BC Chen <rex-bc.chen@...iatek.com>
Cc:     mturquette@...libre.com, sboyd@...nel.org, matthias.bgg@...il.com,
        p.zabel@...gutronix.de, angelogioacchino.delregno@...labora.com,
        chun-jie.chen@...iatek.com, yong.liang@...iatek.com,
        runyang.chen@...iatek.com, linux-kernel@...r.kernel.org,
        allen-kh.cheng@...iatek.com, linux-clk@...r.kernel.org,
        linux-arm-kernel@...ts.infradead.org,
        linux-mediatek@...ts.infradead.org,
        Project_Global_Chrome_Upstream_Group@...iatek.com
Subject: Re: [PATCH 1/7] clk: mediatek: reset: Correct the logic of setting register

Hi,

On Mon, Apr 18, 2022 at 9:22 PM Rex-BC Chen <rex-bc.chen@...iatek.com> wrote:
>

The subject could be written as "Fix written reset bit offset" to make it
more specific.

> Original assert/deassert bit is BIT(0), but it's more resonable to modify
> them to BIT(id % 32) which is based on id.
>
> This patch will not influence any previous driver because the reset is
> only used for thermal. The id (MT8183_INFRACFG_AO_THERM_SW_RST) is 0.
>
> Fixes: 64ebb57a3df6 ("clk: reset: Modify reset-controller driver")
> Signed-off-by: Rex-BC Chen <rex-bc.chen@...iatek.com>

Otherwise,

Reviewed-by: Chen-Yu Tsai <wenst@...omium.org>