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Message-ID: <7hv8v3eidk.fsf@baylibre.com>
Date: Wed, 20 Apr 2022 11:09:59 -0700
From: Kevin Hilman <khilman@...libre.com>
To: Rex-BC Chen <rex-bc.chen@...iatek.com>, rafael@...nel.org,
viresh.kumar@...aro.org, robh+dt@...nel.org, krzk+dt@...nel.org,
matthias.bgg@...il.com
Cc: jia-wei.chang@...iatek.com, roger.lu@...iatek.com,
hsinyi@...gle.com, angelogioacchino.delregno@...labora.com,
linux-pm@...r.kernel.org, devicetree@...r.kernel.org,
linux-kernel@...r.kernel.org, linux-arm-kernel@...ts.infradead.org,
linux-mediatek@...ts.infradead.org,
Project_Global_Chrome_Upstream_Group@...iatek.com,
Rex-BC Chen <rex-bc.chen@...iatek.com>
Subject: Re: [PATCH V3 11/15] cpufreq: mediatek: Link CCI device to CPU
Hi Rex,
Rex-BC Chen <rex-bc.chen@...iatek.com> writes:
> From: Jia-Wei Chang <jia-wei.chang@...iatek.com>
>
> In some MediaTek SoCs, like MT8183, CPU and CCI share the same power
> supplies. Cpufreq needs to check if CCI devfreq exists and wait until
> CCI devfreq ready before scaling frequency.
>
> Before CCI devfreq is ready, we record the voltage when booting to
> kernel and use the max(cpu target voltage, booting voltage) to
> prevent cpufreq adjust to the lower voltage which will cause the CCI
> crash because of high frequency and low voltage.
>
> - Add is_ccifreq_ready() to link CCI device to CPI, and CPU will start
> DVFS when CCI is ready.
> - Add platform data for MT8183.
>
> Signed-off-by: Jia-Wei Chang <jia-wei.chang@...iatek.com>
> Signed-off-by: Rex-BC Chen <rex-bc.chen@...iatek.com>
The solution of keeping the max of the CPU voltage from OPP and boot-up
voltage makes sense until CCI is ready. Thank you for the rework and
the detailed technical explanations.
Reviewed-by: Kevin Hilman <khilman@...libre.com>
Kevin
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