linux-kernel - RE: [PATCH v3 7/9] x86: Add hardware prefetch control support for x86

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Message-ID: <OSBPR01MB2037FFD9250ED3E075E2778080F79@OSBPR01MB2037.jpnprd01.prod.outlook.com>
Date:   Fri, 22 Apr 2022 12:16:18 +0000
From:   "tarumizu.kohei@...itsu.com" <tarumizu.kohei@...itsu.com>
To:     'Thomas Gleixner' <tglx@...utronix.de>,
        "catalin.marinas@....com" <catalin.marinas@....com>,
        "will@...nel.org" <will@...nel.org>,
        "mingo@...hat.com" <mingo@...hat.com>,
        "bp@...en8.de" <bp@...en8.de>,
        "dave.hansen@...ux.intel.com" <dave.hansen@...ux.intel.com>,
        "x86@...nel.org" <x86@...nel.org>, "hpa@...or.com" <hpa@...or.com>,
        "linux-arm-kernel@...ts.infradead.org" 
        <linux-arm-kernel@...ts.infradead.org>,
        "linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
        "fenghua.yu@...el.com" <fenghua.yu@...el.com>,
        "reinette.chatre@...el.com" <reinette.chatre@...el.com>
Subject: RE: [PATCH v3 7/9] x86: Add hardware prefetch control support for x86

> Prefetch control is supported on a lot of CPU models and all except Xeon PHI have
> the same MSR layout. ATOMs do not support L2_ACL and DCU_IP, but that's it. So
> there is absolutely nothing broadwell specific here.
> 
> Why do we need six explicit functions, which are pretty much copy and paste?

There is no special reason for them. My design was not good.

> The only difference is the bit they operate on. It's just a matter of proper wrapper
> structs.
> 
> See? One show() and one store() function which operates directly at the attribute
> level and supports all known variants of bits in the control MSR. No magic global
> constants, no visible management, no hardcoded type/level relations... Simple
> and straight forward.
> 
> All what the core code needs to do is to populate the attributes in the
> sys/.../cache/index$N/ directories when level and type matches.
> 
> I'm pretty sure you can simplify the A64FX code in a very similar way.

Thank you for showing me a concrete example. The implementation image
is now clear. With this in mind, I would like to simplify the core,
x86 and A64FX codes.