linux-kernel - RE: [PATCH v3 1/9] drivers: base: Add hardware prefetch control core driver

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Message-ID: <OSBPR01MB20378E97DE0CB45ABB5E677680F79@OSBPR01MB2037.jpnprd01.prod.outlook.com>
Date:   Fri, 22 Apr 2022 12:10:57 +0000
From:   "tarumizu.kohei@...itsu.com" <tarumizu.kohei@...itsu.com>
To:     'Thomas Gleixner' <tglx@...utronix.de>,
        "catalin.marinas@....com" <catalin.marinas@....com>,
        "will@...nel.org" <will@...nel.org>,
        "mingo@...hat.com" <mingo@...hat.com>,
        "bp@...en8.de" <bp@...en8.de>,
        "dave.hansen@...ux.intel.com" <dave.hansen@...ux.intel.com>,
        "x86@...nel.org" <x86@...nel.org>, "hpa@...or.com" <hpa@...or.com>,
        "linux-arm-kernel@...ts.infradead.org" 
        <linux-arm-kernel@...ts.infradead.org>,
        "linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
        "fenghua.yu@...el.com" <fenghua.yu@...el.com>,
        "reinette.chatre@...el.com" <reinette.chatre@...el.com>
CC:     Greg Kroah-Hartman <gregkh@...uxfoundation.org>,
        "Rafael J. Wysocki" <rafael@...nel.org>
Subject: RE: [PATCH v3 1/9] drivers: base: Add hardware prefetch control core
 driver

Thanks for the comment.

> This is A64FX specific.
> This is x86 specific.
> This is A64FX specific.
> 
> So why is this in generic code and why needs x86 to populate the A64FX bits and
> make them invisible? Same the other way round.

As you commented, current generic code includes things that are not
needed outside of specific hardware.
 
> Now imagine a few other [sub]architectures come around and add their specific
> prefetcher control knobs, strings and whatever. That's going to be unmaintainable
> in no time.
> 
> This is not comparable to the cache attributes where the architectures share a
> significant amount of subsets. You just demonstrated that X86 and A64FX share
> not even a single entry.
> 
> The core code should provide infrastructure to manage the [sub]architecture
> specific control files at different cache levels.
> 
> Not more not less.

I understand the risks of the current implementation.

I would like to fix the core code to provide infrastructure to manage
the [sub]architecture specific control files at different cache levels
by also referring to the comments I received at patch 7/9.